a change that might have an effect on the problems some have seen
with older chips, it looks like the driver may have mistakenly thought
there was an SIA when there isn't.
This driver includes the following patches submitted by:
1.0 Hideyuki Suzuki <hideyuki@sat.t.u-tokyo.ac.jp>
Japanese Cable support
2.0 Keith Sklower <sklower@CS.Berkeley.EDU>
Minor update to the BSDI section so it compiles cleanly on BSDI
3.0 Joao Carlos Mendes Luis <jonny@coppe.ufrj.br>
ioctl interface to select video format , NTSC, PAL, etc...
overruns (not that it was a problem, but it could be):
1) Doubled the number of receive buffers in the DMA chain to 64.
2) Do packet receive processing before transmit in the interrupt routine.
if it is in 10Mbps mode and gets certain types of garbage prior to
the packet header. The work-around involves reprogramming the
multicast filter if nothing is received in some number of seconds
(currently set at 15). As a side effect, implemented complete support
for multicasting rather than the previous 'receive all multicasts'
hack, since we now have the ability to program the filter table.
Fixed a serious bug which crept in with the timeout() changes;
the cookie was only saved on the first timeout() call in fxp_init()
and wasn't updated in the most common place in fxp_stats_update()
when the timeout was rescheduled. This bug would have resulted in
an eventual panic if fxp_stop() was called (which happens when any
interface flags are changed, for example).
Fixed a bug in Alpha support that would have caused the TxCB
descriptor chain to span a page boundry, causing serious problems
if the pages didn't happen to be contiguous.
Removed some gratuitous bit masking that was left over from an
older implementation.
Fixed a bug where too much was copied from the configuration
template, spilling over into memory that followed it.
Fixed handling of if_timer...it was cleared too early in some cases.
of multiple PCI IDE controllers(Dyson), and some updates and cleanups from
John Hood, who originally made our IDE DMA stuff work :-).
I have run tests with 7 IDE drives connected to my system, all in DMA
mode, with no errors. Modulo any bugs, this stuff makes IDE look
really good (within it's limitations.)
Submitted by: John Hood <cgull@smoke.marlboro.vt.us>
rather than extracting the diff from Mark's patch, but it turns out that
I was freeing one allocation twice due to a previous cut/paste braino.
My botch, not Mark's.
Pointed out by: Mark Valentine <mv@pobox.com>
large (over 4KB) softc struct. The descriptor array is accessed by
busmaster dma and must be physically contiguous in memory. malloc() of
a block greater than a page is only virtually contiguous, and not
necessarily physically contigious.
contigmalloc() could do this, but that is a bit on the overkill side.
I'm not sure of the origins of the problem report and diagnosis, I learned
of the problem via mail forwarded from Jim Shankland <jas@flyingfox.com>.
Jim said that Matt Thomas's workaround was to reduce the number of
transmit descriptors from 128 to 32, but I was concerned that it might
cost performance. Anyway, this change is my fault, not Jim's. :-)
Reviewed by: davidg
* lots of fixes to error handling-- mostly works now
* improve DMA timing config for Triton chipsets-- PIIX4 and UDMA drive
still untested
* generally improve DMA config in many ways-- mostly cleanup
* clean up boot-time messages
* rewrite PRD generation algorithm
* first wd timeout is now longer, to handle drive spinup
Submitted by: John Hood <cgull@smoke.marlboro.vt.us>
could cause a solid system lockup in the driver attach:
These chips do not abort an access to the internal SRAM, when
the driver set the software reset bit in the istat register. But
the chip will never acknowledge the requested PCI bus transfer
in the situation, causing an infinite wait and a lockout of other
bus-masters.
The problem has been reported for rev 0x11 of the 53c825a and
rev 0x01 of the 53c875.
Revisions 0x13 of the 53c825a and 0x03 of the 53c875 are known
to support SRAM accesses, even in the software reset state.
- Do not malloc SCRIPTS memory for those parts of the microcode that
are to be loaded into the on-chip SRAM of the 53c825a or 875 ...
- Modify ncr_chip_lookup to make adding new entries easier.
- Disable use of on-chip SRAM for the 53c825 rev 0x10 to 0x12, since
there seems to be a problem with rev 0x11, while 0x13 is known to
work. (Tested by Chuck Robey <chuckr@glue.umd.edu>).
This code will be merged into 2.2-stable after a few more days of
testing in -current.
mod makes sure that the Natoma chipset is set into the correct mode. In
the case of my P6DNF, when booting a UP kernel, I see a substantial improvement
in the latency of certain operations. It appears that the cache hit
latency is curiously improved the most, per lat_mem_rd.
found by taking my HP800CT apart, perusing HPs (Very good!) service
manual and inference from a bad gif file I found in Finland.
Sigh... But it's a nice machine :-)
certain variants of the NCR chip from FE_CACHE_SET: FE_CLSE (enable
cache-line size register) and FE_ERMP (enable read-multiple). They
will be re-enabled, if a fix for the underlying problem (a restriction
in the memory to memory move logic of some chips) has been implemented.
