Commit Graph

90 Commits

Author SHA1 Message Date
Adrian Chadd
813b73a5a9 Migrate if_arge to use the PLL cpuops.
This has been lightly tested on the AR7161 and AR9132.
2010-08-19 16:29:08 +00:00
Adrian Chadd
303fea5cdc Implement PLL generalisation in preparation for use in if_arge.
* Add a function to write to the relevant PLL register
* Break out the PLL configuration for the AR71XX into the CPU ops,
  lifted from if_arge.c.
* Add the AR91XX PLL configuration ops, using the AR91XX register
  definitions.
2010-08-19 16:25:15 +00:00
Adrian Chadd
44c5dea1d8 add the PLL set functions to cpuops 2010-08-19 16:15:30 +00:00
Adrian Chadd
88e08e7ce6 Fix mistaken indenting. 2010-08-19 12:52:49 +00:00
Adrian Chadd
c4df93502d Add some initial AR724X chipset support.
This is untested but should at least allow an AR724X to boot.

The current code is lacking the detail needed to expose the PCIe bus.
It is also lacking any NIC, PLL or flush/WB code.
2010-08-19 11:53:55 +00:00
Adrian Chadd
f3135331c6 Add initial Atheros AR91XX support.
This works well enough to bring a system up to single-user mode
using an MDROOT.

Known Issues:

* The EHCI USB doesn't currently work and will panic the kernel during
  attach.
* The onboard ethernet won't work until the PLL routines have been
  fleshed out and shoe-horned into if_arge.
* The WMAC device glue (and quite likely the if_ath support)
  hasn't yet been implemented.
2010-08-19 11:40:10 +00:00
Adrian Chadd
c2ddd1eef7 Add missing licence. 2010-08-19 11:18:50 +00:00
Adrian Chadd
8d19ed7cbc style(9) pick from imp@ . 2010-08-19 11:16:52 +00:00
Adrian Chadd
292899c376 Remove now unused 'reg'. 2010-08-19 02:15:39 +00:00
Adrian Chadd
6f96ebf309 Initialise the USB system using cpuops rather than the AR71XX specific method. 2010-08-19 02:14:53 +00:00
Adrian Chadd
1d11005672 Migrate the CPU reset path to use the new cpuops. 2010-08-19 02:12:04 +00:00
Adrian Chadd
5b877d30b5 Remove the now-unused DDR flush register value. 2010-08-19 02:10:05 +00:00
Adrian Chadd
23f10186b5 Make the PCI initialisation path use the new cpuops rather than directly
programming the reset register.
2010-08-19 02:05:16 +00:00
Adrian Chadd
fd11fd075a Make if_arge use the new cpuops rather than hard coding the DDR flush registers. 2010-08-19 02:04:35 +00:00
Adrian Chadd
70bd9230d1 Preparation work for supporting the AR91xx and AR724x.
* Implement a SoC probe function, from Linux, which determines the
  SoC family, type and revision. This only probes the AR71xx series
  SoC and (currently) panics on others.

* Migrate some of the AR71XX specific hardware init (USB device, determining
  system frequencies) into using the cpuops introduced in an earlier commit.
  Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring,
  Ethernet PLL setup, other things I've likely missed) will be introduced in
  subsequent commits.

Reviewed by:	imp@
Obtained from:	(partially) Linux
2010-08-19 02:03:12 +00:00
Adrian Chadd
5429211e0a Add a DDR flush function, inspired by both Linux and if_arge.c. 2010-08-18 09:11:45 +00:00
Adrian Chadd
3692b33ce3 Add a further register definition for USB device initialisation.
Obtained from:	Linux
2010-08-18 08:22:58 +00:00
Adrian Chadd
4d843b15ca Bring over the first cut of the Atheros-specific SoC operations.
Each of these SoCs have different devices, different hardware initialisation
methods and, quite likely, different quirks. These functions will abstract
out the SoC differences and keep these differences out of the drivers (eg
USB init, if_arge, etc.)
2010-08-18 08:22:09 +00:00
Adrian Chadd
7f8184068f Import initial AR91XX and AR724X CPU register definitions.
Obtained from:	Linux
2010-08-18 00:26:14 +00:00
Oleksandr Tymoshenko
d8484ec681 - Add interrupts counter for PCI devices 2010-08-05 21:31:29 +00:00
Adrian Chadd
ff97a64735 Add TX-path aligned/unaligned stats for if_arge. 2010-07-08 15:20:57 +00:00
Adrian Chadd
ef54d27641 Address PR kern/148307 - fix if_ath TX mbuf alignment/size constraint checks
The existing code only checked the alignment of the first mbuf and
didn't enforce the size constraints.

This commit introduces a simple function to check the alignment and
size of all mbufs in the list. This fixes the initial issue in the
PR.

PR: kern/148307
Reviewed by: gonzo@
2010-07-08 14:59:32 +00:00
Adrian Chadd
d06458f7f7 Introduce a sysctl block for if_arge and, for now, a blank debug sysctl
placeholder for later.

Add in a missing FreeBSD ID string.
2010-07-08 14:34:15 +00:00
Adrian Chadd
ac35b90587 Fix the CS line definitions. These bits are for the CS2/CS1 lines
rather than CS1/CS0.

This has been tested on the Ubiqiti Routerstation Pro board.
2010-07-07 15:05:44 +00:00
Adrian Chadd
7107f92fd6 Comment about the shared pins I know about. 2010-06-24 05:17:21 +00:00
Adrian Chadd
e3ded4845c AR71XX GPIO register definitions.
Reviewed by:	gonzo@
2010-06-23 03:59:26 +00:00
Adrian Chadd
7bc1af9566 Extend the AR71XX watchdog debugging and data.
* Add some per-device sysctl entries which record the watchdog state -
  whether it is armed; whether the last reboot was due to the watchdog.
* Add a per-device sysctl debug flag to enable logging watchdog arming/
  disarming.

Reviewed by:	gonzo@
2010-06-19 12:12:39 +00:00
Maxim Sobolev
e50d35e6c6 Add new tunable 'net.link.ifqmaxlen' to set default send interface
queue length. The default value for this parameter is 50, which is
quite low for many of today's uses and the only way to modify this
parameter right now is to edit if_var.h file. Also add read-only
sysctl with the same name, so that it's possible to retrieve the
current value.

MFC after:	1 month
2010-05-03 07:32:50 +00:00
Oleksandr Tymoshenko
d51a8afbfe - Fix mutex type for miibus_mtx: it's not spinlock, it's def lock 2010-04-08 18:32:13 +00:00
Alexander Kabaev
779fea6010 Define DMA_RX_STATUS_OVERFLOW with correct value.
The RX overflow is reported in bit 2 on real hardware and Linux driver
for the same device already has this defined correctly.
This fixes frequent interrupt storms seen on RouterStation Pro boards.

Discussed with:	gonzo
2010-02-19 17:37:46 +00:00
Oleksandr Tymoshenko
c1517c0df5 - Increase timeouts to 100 milliseconds, 1 millisecond is definitely not
enough for PCI controller to get into shape

Thanks to: adrian@
2010-01-28 21:55:56 +00:00
Oleksandr Tymoshenko
d86043b594 - Call post-boot fixup function in order to get proper static
symbols resolving in DDB
- When zeroing .bss/.sbss do not round end address to page boundary,
    it's not neccessary and might destroy data pased by trampoline or
    boot loader
2010-01-25 00:44:05 +00:00
Warner Losh
657a57d730 Update from old DDB convetion to initialize debugger to new KDB way.
Always call kdb_init().  If we have KDB enabled, then provide a handy
place to break to the debugger.
2010-01-23 00:18:12 +00:00
Oleksandr Tymoshenko
61b1ecf6d3 - Add driver for PCF2123, SPI real time clock/calendar 2010-01-22 22:14:12 +00:00
Oleksandr Tymoshenko
9e3ed0a7fe - Remove unnecessary register writes in activate_device
and deactivate_device
- Save state before attaching driver and restore it when
    detaching
- Clear CLK bit after last bit of byte has been sent over
    the bus providing falling edge for last byte in transfer
- Fix several places where CS0 was always assumed
- Add $FreeBSD$ to ar71xxreg.h
2010-01-21 00:15:59 +00:00
Warner Losh
3ad9e328b8 Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the
BSP.  Provide a missing prototype.
2010-01-09 03:08:22 +00:00
Warner Losh
a096e4b36b Centralize initialization of pcpu, and set curthread early... 2010-01-08 22:48:21 +00:00
Oleksandr Tymoshenko
2839b59a94 - Add intr counters for APB interrupts 2009-11-18 22:53:05 +00:00
Oleksandr Tymoshenko
2b8344b8fa - Handle multiphy MAC case: create interface with
fixed-state media with parameters set via hints
    and configure MAC accordingly to these parameters.
    All the underlying PHY magic is done by boot manager
    on startup. At the moment there is no proper way
    to make active and control all PHYs simultaneously
    from one MII bus and there is no way to associate
    incoming/outgoing packet with specific PHY.
2009-11-12 21:27:58 +00:00
Oleksandr Tymoshenko
445ee40baa - include register definitions for respective controllers 2009-11-12 20:48:04 +00:00
Oleksandr Tymoshenko
bec244c750 - Access to all 5 PHYs goes through registers in MAC0 memory
space, rewrite miibus accessors respectively
2009-11-08 07:26:02 +00:00
Oleksandr Tymoshenko
40a554d7ac - Fix: Wrong register is used for initial value reading 2009-11-06 21:53:38 +00:00
Oleksandr Tymoshenko
6450bdc708 - Fix initialization of PLL registers (different shifts for
arge0/arge1)
- Use base MAC address to generate MACs for arge1 and above
2009-11-06 06:50:45 +00:00
Oleksandr Tymoshenko
d6994d3b0e - Replace dumb cut'n'paste call with not to self (XXX) 2009-11-05 03:54:03 +00:00
Oleksandr Tymoshenko
896ef84ff0 - style(9): replace whitespaces with tabs 2009-11-04 23:34:58 +00:00
Oleksandr Tymoshenko
a0d684a583 - Remove noisy "Implement me" stubs
- Handle SIOCSIFFLAGS ioctl
2009-11-04 23:33:36 +00:00
Randall Stewart
8fae280afb With this commit our friend RMI will now compile. I have
not tested it and the chances of it running yet are about
ZERO.. but it will now compile. The hard part now begins,
 making it run ;-)
2009-10-30 08:53:11 +00:00
Oleksandr Tymoshenko
12dfccb876 - Fix build with DEVICE_POLLING enabled 2009-10-30 01:40:32 +00:00
Andrew Thompson
3c2330f2e4 Parse and save the command line passed in from RedBoot (exec -c "xxx") and also
the board specific environment variables.

This is not ar71xx specific and should be shared better.
2009-10-28 21:27:56 +00:00
Randall Stewart
3f907e3338 Does 4 things:
1) Adds future RMI directories
2) Places intr_machdep.c in specfic files.arch pointing to the generic
   intr_machdep.c.  This allows us to have an architecture dependant intr_machdep.c
   (which we will need for RMI) in the machine specific directory
3) removes intr_machdep.c from files.mips
4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We
   may need to look at finding a better place to put this. But first I want to
   get this thing compiling.
2009-10-15 21:03:32 +00:00