Commit Graph

3 Commits

Author SHA1 Message Date
adrian
b33e16745c [atheros] Teach the QCA955x SoC code about the new hints stuff. 2018-02-01 22:00:05 +00:00
adrian
8c2676b7e0 Add pcb1 to the QCA955x.
The Tp-link Archer-C7v2 unit has a QCA9558 internally but hangs the
QCA988x 11ac PCIe NIC off of PCI RC #1, not #0.

So I actually finally /do/ have a board to verify whether PCIe is working.
Grr.

Tested:

* TP-Link Archer-C7v2.
2015-07-03 06:06:44 +00:00
adrian
0753bc3ad1 Bring over the initial QCA955x SoC support framework.
This is enough to bring up the basic SoC support.

What works thus far:

* The mips74k core, pll setup, and UART (or else well, stuff would
  be really difficult..)
* both USB 2.0 EHCI controllers
* on-board 2GHz 3x3 wifi (the other variant has 2GHz/5GHz wifi on-chip);
* arge0 - not yet sure why arge1 isn't firing off interrupts and thus
  handling traffic, but I will soon figure it out and fix it here.

Tested:

* AP135 reference design, QCA9558 SoC, pretending to be an 11n
  2GHz AP.

TODO:

* There's an interrupt mux hooking up devices to IP2 and IP3 - but it's
  not a read-and-clear or write-to-clear register.  So, trying to use it
  naively like I have been ends up with massive interrupt storms.
  For now the things that share those interrupts can just take them as
  shared interrupts and try to play nice.

* There's two PCIe root complexes /and/ one of them can actually be
  a PCIe device endpoint.  Yes, you heard right.  I have to teach the
  AR724x PCIe bridge code to handle multiple instances with multiple
  memory/irq regions, and then there'll be RC support, but EP support
  isn't on my TODO list.

* I'm not sure why arge1 isn't up and running.  I'll go figure that
  out soon and fix it here.

Thankyou to Qualcomm Atheros for providing me with hardware and
an abundance of documentation about these things.
2015-03-02 02:24:46 +00:00