Commit Graph

9 Commits

Author SHA1 Message Date
Mike Smith
510a809e64 Teach the 'dc' driver how to pick up settings left over by the
SRM on alpha systems.  This is an expedient if not entirely
elegant solution to the problem.

Submitted by:	gallatin
Approved by:	jkh
2000-03-11 05:20:56 +00:00
Robert Watson
c8cf61e182 Introduce ethernet bridge support for if_dc
Approved by:	jkh
2000-03-09 19:28:19 +00:00
Bill Paul
f43d9309a5 Add support for DM9102A boards with Davicom DM9801 HomePNA PHYs. 2000-01-24 17:19:37 +00:00
Bill Paul
88d739dc5f Add support for the Davicom DM9102A 10/100 ethernet controller chip.
This is just to make sure we initialize the chip correctly: we need to
make the sure the port select bit in CSR6 is set properly so that we
use the internal PHY for 10/100 support. (The eval boards I have also
include an external HomePNA PHY, but I need to play with that more
before I can support it.)
2000-01-19 19:03:08 +00:00
Bill Paul
fda39fd069 Reintroduce the dc_coal() workaround routine for coalescing outbound
packets into a single buffer, and set the DC_TX_COALESCE flag for the
Davicom DM9102 chip. I thought I had escaped this problem, but... This
chip appears to silently corrupt or discard transmitted frames when
using scatter/gather DMA (i.e. DMAing each packet fragment in place
with a separate descriptor). The only way to insure reliable transmission
is to coalesce transmitted packets into a single cluster buffer. (There
may also be an alignment constraint here, but mbuf cluster buffers are
naturally aligned on 2K boundaries, which seems to be good enough.)

The DM9102 driver for Linux written by Davicom also uses this workaround.
Unfortunately, the Davicom datasheet has no errata section describing
this or any other apparently known defect.

Problem noted by: allan_chou@davicom.com.tw
2000-01-12 22:24:05 +00:00
Bill Paul
73bf949c34 It appears that under certain circumstances that I still can't quite pin
down, the dc driver and receiver can fall out of sync with one another,
resulting in a condition where the chip continues to receive packets
but the driver never notices. Normally, the receive handler checks each
descriptor starting from the current producer index to see if the chip
has relinquished ownership, indicating that a packet has been received.
The driver hands the packet off to ether_input() and then prepares the
descriptor to receive another frame before moving on to the next
descriptor in the ring. But sometimes, the chip appears to skip a
descriptor. This leaves the driver testing the status word in a descriptor
that never gets updated. The driver still gets "RX done" interrupts but
never advances further into the RX ring, until the ring fills up and the
chip interrupts again to signal an error condition. Sometimes, the
driver will remain in this desynchronized state, resulting in spotty
performance until the interface is reset.

Fortunately, it's fairly simple to detect this condition: if we call
the rxeof routine but the number of received packets doesn't increase,
we suspect that there could be a problem. In this case, we call a new
routine called dc_rx_resync(), which scans ahead in the RX ring to see
if there's a frame waiting for us somewhere beyond that the driver thinks
is the current producer index. If it finds one, it bumps up the index
and calls the rxeof handler again to snarf up the packet and bring the
driver back in sync with the chip. (It may actually do this several times
in the event that there's more than one "hole" in the ring.)

So far the only card supported by if_dc which has exhibited this problem
is a LinkSys LNE100TX v2.0 (82c115 PNIC II), and it only seems to happen
on one particular system, however the fix is general enough and has low
enough overhead that we may as well apply it for all supported chipsets.
I also implemented the same fix for the 3Com xl driver, which is apparently
vulnerable to the same problem.

Problem originally noted and patch tested by: Matt Dillon
2000-01-03 15:28:47 +00:00
Bill Paul
91cc2adb2e Fix some problems reported by Mike Pritchard:
- Add a flag DC_TX_INTR_ALWAYS which causes the transmit code to
  request a TX done interrupt for every packet. The PNIC seems to need
  this to insure that the sent TX buffers get reaped in a timely fashion.

- Try to unreset the SIA as soon as possible after resetting the whole
  chip.

- Change dcphy to support either 10/100 or 10Mbps only NICs. The
  built-in 21143 ethernet in Compaq Presario machines is 10Mbps only
  and it doesn't work right if we try to advertise 100Mbps modes during
  autoneg. When restricted to only 10mbps modes, it works fine.

  Note that for now, I detect this condition by checking the PCI
  subsystem ID on this NIC (which has a Compaq vendor/device ID).
  Yes, I know that's what the SROM is supposed to be for. I'm deliberately
  ignoring the SROM wherever possible. Sue me.

The latter two fixes allow if_dc to work correctly with the built-in
ethernet on certain Compaq Presario boxes. There are liable to be quite
a few people using these as their home systems who might want to try
FreeBSD; may as well be nice to them.

Now if anybody out there has an Alpha miata with 10Mbps ethernet and
can show me the output from pciconf -l on their system, I'd be grateful.
1999-12-13 21:45:13 +00:00
Bill Paul
d675147e39 Tweak the DC_REDUCED_MII_POLL code in dc_mii_tick() for the DC_IS_INTEL()
case. The idea is to reduce how often we call mii_tick(), however currently
it may not be called often enough, which prevents autonegotiation from
being driven correctly.

This should improve the chances of successfully autonegotiating media
settings on non-MII 21143 NICs. (Still waiting for confirmation from
some testers, but the code is clearly wrong in any case.)
1999-12-07 19:18:41 +00:00
Bill Paul
96f2e892a7 Add the if_dc driver and remove all of the al, ax, dm, pn and mx drivers
which it replaces. The new driver supports all of the chips supported
by the ones it replaces, as well as many DEC/Intel 21143 10/100 cards.

This also completes my quest to convert things to miibus and add
Alpha support.
1999-12-04 17:41:31 +00:00