Commit Graph

10632 Commits

Author SHA1 Message Date
jhb
ca8d347695 Add a new 'pmap_invalidate_cache()' to flush the CPU caches via the
wbinvd() instruction.  This includes a new IPI so that all CPU caches on
all CPUs are flushed for the SMP case.

MFC after:	1 month
2006-05-01 21:36:47 +00:00
peter
4db7dec298 Using an idea from Stephan Uphoff, use the empty pte's that correspond
to the unused kva in the pv memory block to thread a freelist through.
This allows us to free pages that used to be used for pv entry chunks
since we can now track holes in the kva memory block.

Idea from:  ups
2006-05-01 21:22:38 +00:00
peter
b5fd7cea55 Fix missing changes required for the amd64->i386 conversion. Add the
missing VM_ALLOC_WIRED flags to vm_page_alloc() calls I added.

Submitted by:  alc
2006-05-01 19:57:00 +00:00
marcel
193a6144b9 Rewrite of puc(4). Significant changes are:
o  Properly use rman(9) to manage resources. This eliminates the
   need to puc-specific hacks to rman. It also allows devinfo(8)
   to be used to find out the specific assignment of resources to
   serial/parallel ports.
o  Compress the PCI device "database" by optimizing for the common
   case and to use a procedural interface to handle the exceptions.
   The procedural interface also generalizes the need to setup the
   hardware (program chipsets, program clock frequencies).
o  Eliminate the need for PUC_FASTINTR. Serdev devices are fast by
   default and non-serdev devices are handled by the bus.
o  Use the serdev I/F to collect interrupt status and to handle
   interrupts across ports in priority order.
o  Sync the PCI device configuration to include devices found in
   NetBSD and not yet merged to FreeBSD.
o  Add support for Quatech 2, 4 and 8 port UARTs.
o  Add support for a couple dozen Timedia serial cards as found
   in Linux.
2006-04-28 21:21:53 +00:00
peter
725e9bf143 Interim fix for pmap problems I introduced with my last commit.
Remove the code to dyanmically change the pv_entry limits.  Go back
to a single fixed kva reservation for pv entries, like was done
before when using the uma zone.  Go back to never freeing pages
back to the free pool after they are no longer used, just like
before.

This stops the lock order reversal due to aquiring the kernel map
lock while pmap was locked.

This fixes the recursive panic if invariants are enabled.

The problem was that allocating/freeing kva causes vm_map_entry
nodes to be allocated/freed.  That can recurse back into pmap as
new pages are hooked up to kvm and hence all the problem.
Allocating/freeing kva indirectly allocate/frees memory.

So, by going back to a single fixed size kva block and an index,
we avoid the recursion panics and the LOR.

The problem is that now with a linear block of kva, we have no
mechanism to track holes once pages are freed.  UMA has the same
problem when using custom object for a zone and a fixed reservation
of kva.  Simple solutions like having a bitmap would work, but would
be very inefficient when there are hundreds of thousands of bits
in the map.  A first-free pointer is similarly flawed because pages
can be freed at random and the first-free pointer would be rewinding
huge amounts.  If we could allocate memory for tree strucures or
an external freelist, that would work.  Except we cannot allocate/free
memory here because we cannot allocate/free address space to use
it in.  Anyway, my change here reverts back to the UMA behavior of
not freeing pages for now, thereby avoiding holes in the map.

ups@ had a truely evil idea that I'll investigate.  It should allow
freeing unused pages again by giving us a no-cost way to track the
holes in the kva block.  But in the meantime,  this should get people
booting with witness and/or invariants again.

Footnote: amd64 doesn't have this problem because of the direct map
access method.  I'd done all my witness/invariants testing there.  I'd
never considered that the harmless-looking kmem_alloc/kmem_free calls
would cause such a problem and it didn't show up on the boot test.
2006-04-28 19:05:08 +00:00
sobomax
1e82b0de25 Unbreak pc98. Sorry... 2006-04-28 03:38:23 +00:00
alc
da3edd51a2 In general, bits in the page directory entry (PDE) and the page table
entry (PTE) have the same meaning.  The exception to this rule is the
eighth bit (0x080).  It is the PS bit in a PDE and the PAT bit in a
PTE.  This change avoids the possibility that pmap_enter() confuses a
PAT bit with a PS bit, avoiding a panic().

Eliminate a diagnostic printf() from the i386 pmap_enter() that serves
no current purpose, i.e., I've seen no bug reports in the last two
years that are helped by this printf().

Reviewed by: jhb
2006-04-27 21:26:25 +00:00
scottl
8bb256220b Add the rr232x driver to the default kernels. 2006-04-27 20:58:24 +00:00
sobomax
b5181c79ef In the case when reset via keyboard controller doesn't work for some reason
(i.e. no keyboard controller present), try two other common methods for
resetting i386 machine - pci reset and port 0x92 fast reset. Only if neither
works warn user and resort to "unmap entire address space and hope for good"
hack. This makes my MacBook Pro rebooting just fine and should also help
other legacy-free hardware out there.

Also, disable interrupts unconditionally in cpu_reset_real(), since we don't
want any interference.

MFC after:	1 week
2006-04-27 05:18:26 +00:00
delphij
fc73c02211 Fix build on i386 2006-04-27 05:02:21 +00:00
peter
8165896908 MFamd64: shrink pv entries from 24 bytes to about 12 bytes. (336 pv entries
per page = effectively 12.19 bytes per pv entry after overheads).
Instead of using a shared UMA zone for 24 byte pv entries (two 8-byte tailq
nodes, a 4 byte pointer, and a 4 byte address), we allocate a page at a
time per process.  This provides 336 pv entries per process (actually, per
pmap address space) and eliminates one of the 8-byte tailq entries since
we now can track per-process pv entries implicitly.  The pointer to
the pmap can be eliminated by doing address arithmetic to find the metadata
on the page headers to find a single pointer shared by all 336 entries.
There is an 11-int bitmap for the freelist of those 336 entries.

This is mostly a mechanical conversion from amd64, except:
* i386 has to allocate kvm and map the pages, amd64 has them outside of kvm
* native word size is smaller, so bitmaps etc become 32 bit instead of 64
* no dump_add_page() etc stuff because they are in kvm always.
* various pmap internals tweaks because pmap uses direct map on amd64 but
  on i386 it has to use sched_pin and temporary mappings.

Also, sysctl vm.pmap.pv_entry_max and vm.pmap.shpgperproc are now
dynamic sysctls.  Like on amd64, i386 can now tune the pv entry limits
without a recompile or reboot.

This is important because of the following scenario.   If you have a 1GB
file (262144 pages) mmap()ed into 50 processes, that requires 13 million
pv entries.  At 24 bytes per pv entry, that is 314MB of ram and kvm, while
at 12 bytes it is 157MB.  A 157MB saving is significant.

Test-run by:  scottl (Thanks!)
2006-04-26 21:49:20 +00:00
jkim
18e73c2320 Check if reported HTT cores are physical cores. This commit does not
affect AMD CPUs at all because HTT bit is disabled earlier.  Intel
multicore CPUs and ULE scheduler may be affected.
2006-04-25 00:06:37 +00:00
jkim
eefd58df92 Add another Intel CPU feature flag, xTPR (Send Task Priority Messages). 2006-04-24 22:56:57 +00:00
jkim
6b218fc19f Check if deterministic cache parameters leaf is valid before use. 2006-04-24 22:23:52 +00:00
cperciva
900c118819 Adjust dangerous-shared-cache-detection logic from "all shared data
caches are dangerous" to "a shared L1 data cache is dangerous".  This
is a compromise between paranoia and performance: Unlike the L1 cache,
nobody has publicly demonstrated a cryptographic side channel which
exploits the L2 cache -- this is harder due to the larger size, lower
bandwidth, and greater associativity -- and prohibiting shared L2
caches turns Intel Core Duo processors into Intel Core Solo processors.

As before, the 'machdep.hyperthreading_allowed' sysctl will allow even
the L1 data cache to be shared.

Discussed with:	jhb, scottl
Security:	See FreeBSD-SA-05:09.htt for background material.
2006-04-24 21:17:01 +00:00
delphij
da32f1fb9a Move AHC_REG_PRETTY_PRINT and AHD_REG_PRETTY_PRINT below
their corresponding devices.
2006-04-24 08:44:34 +00:00
peter
3fd2125c99 Merge minidumps from amd64 where they were originally developed.
Major differences:
 * since there is no direct map region, there is no custom uma memory
   allocator to modify to include its pages in the dumps.
 * Various data entries are reduced from 64 bit to 32 bit to match the
   native size.

dump_add_page() and dump_drop_page() are still present in case one wants to
arrange for arbitary pages to be dumped.  This is of marginal use though
because libkvm+kgdb cannot address physical memory that isn't mapped into
kvm.
2006-04-21 04:28:43 +00:00
imp
2a2593f381 Set the rid of the resource we're about to return to the user. 2006-04-20 04:10:27 +00:00
cperciva
51d1ca0f6e Correct a local information leakage bug affecting AMD FPUs.
Security:	FreeBSD-SA-06:14.fpu
2006-04-19 07:00:19 +00:00
iwasaki
0613b693d0 Import ACPI Dock Station support. Note that this is still very young.
Additional detach implementaions (or maybe improvement) for other
deivce drivers is required.

Reviewed by:	njl, imp
MFC after:	1 week
2006-04-15 12:31:34 +00:00
alc
a7e3d6f83b Retire pmap_track_modified(). We no longer need it because we do not
create managed mappings within the clean submap.  To prevent regressions,
add assertions blocking the creation of managed mappings within the clean
submap.

Reviewed by: tegge
2006-04-12 04:22:52 +00:00
ps
cc2c59e66f Hook bce up to the build 2006-04-10 20:04:22 +00:00
jhb
dca0aae557 - Don't set CR0_NE and CR0_MP in npx_probe() as they are already set
earlier in cpu_setregs().
- If we know this CPU has a FPU via cpuid, then just assume the INT16
  interface and make the npx device quiet to not clutter the dmesg.  This
  is true for all Pentium and later CPUs and even some of the later 486dx
  CPUs.

Reviewed by:	bde
Tested by:	ps
MFC after:	1 week
2006-04-06 17:17:45 +00:00
jhb
1dfdfa5677 Cache the value of the lower half of each I/O APIC redirection table entry
so that we only have to do an ioapic_write() instead of an ioapic_read()
followed by an ioapic_write() every time we mask and unmask level triggered
interrupts.  This cuts the execution time for these operations roughly in
half.

Profiled by:	Paolo Pisati <p.pisati@oltrelinux.com>
MFC after:	1 week
2006-04-05 20:43:19 +00:00
jkoshy
33b6f0c5ea Freshen a comment.
Reviewed by:	jhb
2006-04-04 02:26:45 +00:00
marcel
8278e2d5fb Eliminate HAVE_STOPPEDPCBS. On ia64 the PCPU holds a pointer to the
PCB in which the context of stopped CPUs is stored. To access this
PCB from KDB, we introduce a new define, called KDB_STOPPEDPCB. The
definition, when present, lives in <machine/kdb.h> and abstracts
where MD code saves the context. Define KDB_STOPPEDPCB on i386,
amd64, alpha and sparc64 in accordance to previous code.
2006-04-03 22:51:47 +00:00
peter
0f363b7d24 Remove the unused sva and eva arguments from pmap_remove_pages(). 2006-04-03 21:16:10 +00:00
alc
af01e3f809 Introduce pmap_try_insert_pv_entry(), a function that conditionally creates
a pv entry if the number of entries is below the high water mark for pv
entries.

Use pmap_try_insert_pv_entry() in pmap_copy() instead of
pmap_insert_entry().  This avoids possible recursion on a pmap lock in
get_pv_entry().

Eliminate the explicit low-memory checks in pmap_copy().  The check that
the number of pv entries was below the high water mark was largely
ineffective because it was located in the outer loop rather than the
inner loop where pv entries were allocated.  Instead of checking, we
attempt the allocation and handle the failure.

Reviewed by: tegge
Reported by: kris
MFC after: 5 days
2006-04-02 05:45:05 +00:00
emax
bce2a6b523 Add kbdmux(4) to GENERIC
Requested by:	scottl
2006-03-31 19:03:37 +00:00
scottl
725c458dc3 Hook the MFI driver up to the build. 2006-03-29 09:57:22 +00:00
des
af5e05fb0b Use wrapper macros for atomic pointer operations in order to perform the
correct casts.  This should probably be merged to other architectures.
2006-03-28 14:34:48 +00:00
jhb
3718b3713e If the XSDT address in the RSDP for an ACPI 2.0 machine is NULL, then fall
back to using the RSDT instead.  ACPI-CA already follows this same strategy
as a workaround for yet another instance of brain-damaged BIOS writers.

PR:		i386/93963
Submitted by:	Masayuki FUKUI <fukui.FreeBSD@fanet.net>
2006-03-27 15:59:48 +00:00
alc
108c9331c3 Eliminate unnecessary invalidations of the entire TLB by pmap_remove().
Specifically, on mappings with PG_G set pmap_remove() not only performs
the necessary per-page invlpg invalidations but also performs an
unnecessary invalidation of the entire set of non-PG_G entries.

Reviewed by: tegge
2006-03-21 18:07:42 +00:00
davidxu
9f834e1bd5 Remove stale KSE code.
Reviewed by: alc
2006-03-21 06:46:27 +00:00
jhb
e11865e4b1 Drop some unneeded casts since we program the kernel in C rather than C++. 2006-03-20 19:39:08 +00:00
netchild
39276e2b1e regen 2006-03-18 20:49:01 +00:00
netchild
d1db96cb48 Fixup some problems in my previous commit (COMPAT_43).
Pointyhat to:	netchild
2006-03-18 20:47:36 +00:00
netchild
8fd6664412 regen after COMPAT_43 removal 2006-03-18 18:24:38 +00:00
netchild
c1829f604c Get rid of the need of COMPAT_43 in the linuxolator.
Submitted by:	Divacky Roman <xdivac02@stud.fit.vutbr.cz>
Obtained from:	DragonFly (some parts)
2006-03-18 18:20:17 +00:00
jhb
aaa33da2ed Don't allow userland to set hardware watch points on kernel memory at all.
Previously, we tried to allow this only for root.  However, we were calling
suser() on the *target* process rather than the current process.  This
means that if you can ptrace() a process running as root you can set a
hardware watch point in the kernel.  In practice I think you probably have
to be root in order to pass the p_candebug() checks in ptrace() to attach
to a process running as root anyway.  Rather than fix the suser(), I just
axed the entire idea, as I can't think of any good reason _at all_ for
userland to set hardware watch points for KVM.

MFC after:	3 days
Also thinks hardware watch points on KVM from userland are bad:	bde, rwatson
2006-03-14 16:13:55 +00:00
davidxu
651e183fe9 It is not necessary to read %gs twice. 2006-03-10 05:55:26 +00:00
davidxu
b36ad9d674 Fix stack offset to allow gcc's stack aligment code to work correctly.
MFC after: 3 days
2006-03-10 02:54:45 +00:00
jhb
329536bd48 Flip the switch and don't route interrupts to hyperthreads in a HT system.
In at least one benchmark this showed around a 20% performance increase.
If other workloads do benefit from having hyperthreads service interrupts,
we can always make this a loader tunable.

MFC after:	3 days
Tested by:	ps
2006-03-09 16:38:52 +00:00
phk
67fc39f642 Improve the advantech watchdog. 2006-03-06 07:43:28 +00:00
yar
0ac62e02bd Take the functionality contained in the former "options TDFX_LINUX"
into a separate module.  Accordingly, convert the option into a device
named similarly.

Note for MFC: Perhaps the option should stay in RELENG_6 for POLA reasons.

Suggested by:	scottl
Reviewed by:	cokane
MFC after:	5 days
2006-03-03 21:37:38 +00:00
netchild
3d39f08ccd - use a more common style to print memory sizes
- add some more cache sizes (2nd and 3rd level) [1]

Submitted by:	HATANOU Tomomi <hatanou@infolab.ne.jp> [1]
PR:		91328 [1]
2006-03-03 18:54:05 +00:00
rink
c057d8091b Committed the xbox syscons(8)-able console driver.
Reviewed by:    arch@ (no comments)
Approved by:    imp (mentor)
2006-03-03 14:52:57 +00:00
scottl
d849f4e1ca iir works on PAE now. 2006-03-03 04:30:18 +00:00
jhb
3478c467ee Rework how we wire up interrupt sources to CPUs:
- Throw out all of the logical APIC ID stuff.  The Intel docs are somewhat
  ambiguous, but it seems that the "flat" cluster model we are currently
  using is only supported on Pentium and P6 family CPUs.  The other
  "hierarchy" cluster model that is supported on all Intel CPUs with
  local APICs is severely underdocumented.  For example, it's not clear
  if the OS needs to glean the topology of the APIC hierarchy from
  somewhere (neither ACPI nor MP Table include it) and setup the logical
  clusters based on the physical hierarchy or not.  Not only that, but on
  certain Intel chipsets, even though there were 4 CPUs in a logical
  cluster, all the interrupts were only sent to one CPU anyway.
- We now bind interrupts to individual CPUs using physical addressing via
  the local APIC IDs.  This code has also moved out of the ioapic PIC
  driver and into the common interrupt source code so that it can be
  shared with MSI interrupt sources since MSI is addressed to APICs the
  same way that I/O APIC pins are.
- Interrupt source classes grow a new method pic_assign_cpu() to bind an
  interrupt source to a specific local APIC ID.
- The SMP code now tells the interrupt code which CPUs are avaiable to
  handle interrupts in a simpler and more intuitive manner.  For one thing,
  it means we could now choose to not route interrupts to HT cores if we
  wanted to (this code is currently in place in fact, but under an #if 0
  for now).
- For now we simply do static round-robin of IRQs to CPUs when the first
  interrupt handler just as before, with the change that IRQs are now
  bound to individual CPUs rather than groups of up to 4 CPUs.
- Because the IRQ to CPU mapping has now been moved up a layer, it would
  be easier to manage this mapping from higher levels.  For example, we
  could allow drivers to specify a CPU affinity map for their interrupts,
  or we could allow a userland tool to bind IRQs to specific CPUs.

The MFC is tentative, but I want to see if this fixes problems some folks
had with UP APIC kernels on 6.0 on SMP machines (an SMP kernel would work
fine, but a UP APIC kernel (such as GENERIC in RELENG_6) would lose
interrupts).

MFC after:	1 week
2006-02-28 22:24:55 +00:00
cperciva
8a3d42569d Add frequency-voltage tables for Intel 778, 758, 773, 753, and 733J
processors.

Obtained from:	Intel Datasheet 302189-008
2006-02-25 04:55:38 +00:00