Commit Graph

44 Commits

Author SHA1 Message Date
Justin T. Gibbs
cd036e891a ahc_pci.c:
If bus_dma will give us addresses > 32 bits, setup our dma tag
	to accept up to 39bit addresses.

aic7770.c:
	Update the softc directly rather than use an intermediate
	"probe_config" structure.

aic7xxx.c:
	Complete core work to support 39bit addresses for bulk data
	dma operations.  Controller data structures still must reside
	under the 4GB boundary to reduce code/data size in the sequencer
	and related data structures.  This has been tested under Linux
	IA64 and will be tested on IA64 for FreeBSD as soon as our port
	can run there.

	Add bus dmamap synchronization calls around manipulation of
	all controller/kernel shared host data structures.

	Implement data pointer reinitialation for a second data phase
	in a single connection in the kernel rather than bloat the
	sequencer.  This is an extremely rare operation (does it ever
	happen?) and the sequencer implementation was flawed for some
	of the newest chips.

	Don't ever allow our target role to initiate a PPR.  This
	is forbidden by the SCSI spec.

	Add a few missing endian conversions in the ignore wide pointers
	code.  The core has been tested on the PPC under Linux and should
	work for FreeBSD PPC.  As soon as I can test the OSM layer for
	FreeBSD PPC, I will.

	Move some of ahc_softc_init() into ahc_alloc() now that the
	probe_config structure is gone.

	Add a 4GB boundary condition on all of our dma tags.  32bit
	DAC under PCI only works on a single 4GB "page".  Although
	we can cross 4GB on a true 64bit bus, the card won't always
	be installed in one and we can save code space and cost in
	implementing high address support by assuming the high DWORD
	address will never change.

	Add diagnostics to ahc_search_qinfifo().

	Correct a target mode issue with bus resets.  To avoid an
	interrupt storm from a malicious third party holding the
	reset line, the sequencer would defer re-enabling the reset
	interrupt until either a select-out or select-in.  Unfortunately,
	the select-in enable bit is cleared by a bus reset, so a second
	reset will render the card deaf to an initiator's attempts to
	contact it.  We now re-enable bus reset interrupts immediately
	if the target role is enabled.

aic7xxx.h:
	Remove struct ahc_probe_config.

	SCB's now contain a pointer to the sg_map_node so we can perfrom
	bus dma sync operations on the SG list prior to queuing a command.

aic7xxx.reg:
	Register the Perforce ID for this file with the VERSION keyword
	so it is printed in generated files.

	Add the DSCOMMAND1 register which is used to access the high
	DWORD of address bits.

	Add the data pointer reinitialize sequencer interrupt code.

aic7xxx.seq:
	Register the Perforce ID for this file with the VERSION keyword
	so it is printed in generated files.

	Remove code to re-enable the bus reset interrupt after a select-in.
	In target mode we cannot defer this operation as ENSELI is cleared
	by a bus reset.

	Complete 39bit support.

	Generate a sequencer inteerrupt rather than handle the data
	pointers re-initialitation in the sequencer.

	Inline the "seen identify" assertion to save a few cycles.

	Short circuit the update of our residual data if we have
	fully completed a transfer.  The residual is correct from
	our last S/G load operation.

	Short circuit full SDPTR processing if the residual is 0.
	Just mark the transfer as complete.

aic7xxx_93cx6.c:
	Synchronize perforce IDs.

aic7xxx_freebsd.c:
	Complete untested 39bit support.

	Add missing endia conversions.

	Clear our residuals prior to starting a command.  The
	update residual code in the core only sets the residual
	if there is one.

aic7xxx_freebsd.h:
	Modeify ahc_dmamap_sync() macros to take an offset and a length.
	This is how sync operations are performed in NetBSD, and we should
	update our bus dma implementation to match.

aic7xxx_inline.h:
	Add data structure synchronization helper functions.

	Fix a bug in ahc_intr() where we would not clear our unsolicited
	interrupt counter after running our PCI interrupt handler.  This
	may have been the cause of the spurious PCI interrupt messages.

aic7xxx_pci.c:
	Adjust for loss of probe_config structure.

	Guard against bogus 9005 subdevice information as seen on some
	IBM MB configurations.

	Add 39bit address support.

MFC after: 10 days
2001-07-18 21:39:48 +00:00
Matt Jacob
0e300eff0a Don't dereference NULL regs pointer (should mapping I/O ports fail, as
they did for me on an alpha)

Approved by:	gibbs@freebsd.org
MFC after:	2 days
2001-06-21 16:18:27 +00:00
Justin T. Gibbs
58fb7d8e0b ahc_eisa.c:
ahc_pci.c:
	Prepare for making ahc a module by adding module dependency
	and version info.

aic7770.c:
	Remove linux header ifdefs.  The headers are handled differently
	in Linux where local includes (those using "'s instead of <>'s)
	are allowed.

	Don't map our interrupt until after we are fully setup to
	handle interrupts.  Our interrupt line may be shared so
	an interrupt could occur at any time.

aic7xxx.c:
	Remove linux header ifdefs.

	current->curr to avoid Linux's use of current as a
	#define for the current task on some architectures.

	Add a helper function, ahc_assert_atn(), for use in
	message phases we handle manually.  This hides the fact
	that U160 chips with the expected phase matching disabled
	need to have SCSISIGO updated differently.

	if (ahc_check_residual(scb) != 0)
		ahc_calc_residual(scb);
	else
		ahc_set_residual(scb, 0);

       	becomes:

	ahc_update_residual(scb);

	Modify scsi parity error (or CRC error) handling to
	reflect expected phase being disabled on U160 chips.

	Move SELTO handling above BUSFREE handling so we can
	use the new busfree interrupt behavior on U160 chips.

	In ahc_build_transfer_msg() filter the period and ppr_options
	prior to deciding whether a PPR message is required.
	ppr_options may be forced to zero which will effect our
	decision.

	Correct a long standing but latent bug in ahc_find_syncrate().
	We could choose a DT only rate even though DT transfers were
	disabled.  In the CAM environment this was unlikely as CAM
	filters our rate to a non-DT value if the device does not
	support such rates.

	When displaing controller characteristics, include the
	speed of the chip.  This way we can modify the transfer
	speed based on optional features that are enabled/disabled
	in a particular application.

	Add support for switching from fully blown tagged queing
	to just using simple queue tags should the device reject
	an ordered tag.

	Remove per-target "current" disconnect and tag queuing
	enable flags.  These should be per-device and are not
	referenced internally be the driver, so we let the OSM
	track this state if it needs to.

	Use SCSI-3 message terminology.

aic7xxx.h:
	The real 7850 does not support Ultra modes, but there are
	several cards that use the generic 7850 PCI ID even though
	they are using an Ultra capable chip (7859/7860).  We start
	out with the AHC_ULTRA feature set and then check the
	DEVSTATUS register to determine if the capability is really
	present.

	current -> curr

	ahc_calc_residual() is no longer static allowing it to
	be called from ahc_update_residual() in aic7xxx_inline.h.

	Update some serial eeprom definitions for the latest
	BIOS versions.

aic7xxx.reg:
	Add a combined DATA_PHASE mask to the SCSIPHASE register
	definition to simplify some sequencer code.

aic7xxx.seq:
	Take advantage of some performance features available only
	on the U160 chips.  The auto-ack feature allows us to ack
	data-in phases up to the data-fifo size while the sequencer
	is still setting up the DMA engine.  This greatly reduces
	read transfer latency and simplifies testing for transfer
	complete (check SCSIEN only).  We also disable the expected
	phase feature, and enable the new bus free interrupt behavior,
	to avoid a few instructions.

	Re-arrange the Ultra2+ data phase handling to allow us to
	do more work in parallel with the data fifo flushing on a
	read.

	On an SDTR, ack the message immediately so the target can
	prepare the next phase or message byte in parallel with
	our work to honor the message.

aic7xxx_93cx6.c:
	Remove linux header ifdefs.

aic7xxx_freebsd.c:
	current -> curr

	Add a module event handler.

	Handle tag downgrades in our ahc_send_async() handler.
	We won't be able to downgrade to "basic queuing" until
	CAM is made aware of this queuing type.

aic7xxx_freebsd.h:
	Include cleanups.

	Define offsetof if required.

	Correct a few comments.

	Update prototype of ahc_send_async().

aic7xxx_inline.h:
	Implement ahc_update_residual().

aic7xxx_pci.c:
	Remove linux header ifdefs.

	Correct a few product strings.

	Enable several U160 performance enhancing features.

	Modify Ultra capability determination so we will enable
	Ultra speeds on devices with a 7850 PCI id that happen
	to really be a 7859 or 7860.

	Don't map our interrupt until after we are fully setup to
	handle interrupts.  Our interrupt line may be shared so
	an interrupt could occur at any time.
2001-05-15 19:41:12 +00:00
Justin T. Gibbs
6fb77fef4d This is an MFC candidate.
ahc_eisa.c:
	Change aic7770_map_int to take an additional irq parameter.
	Although we can get the irq from the eisa dev under FreeBSD,
	we can't do this under linux, so the OSM interface must supply
	this.

ahc_pci.c:
	Move ahc_power_state_change() to the OSM.  This allows us to
	use a platform supplied function that does the same thing.
	-current will move to the FreeBSD native API in the near
	future.

aic7770.c:
	Sync up with core changes to support Linux EISA.

	We now store a 2 bit primary channel number rather
	than a bit flag that only allows b to be the primary
	channel.   Adjust for this change.

aic7xxx.c:
	Namespace and staticization cleanup.  All exported symbols
	use an "ahc_" prefix to avoid collisions with other modules.

	Correct a logic bug that prevented us from dropping
	ATN during some exceptional conditions during message
	processing.

	Take advantage of a new flag managed by the sequencer
	that indicates if an SCB fetch is in progress.  If so,
	the currently selected SCB needs to be returned to the
	free list to prevent an SCB leak.  This leak is a rarity
	and would only occur if a bus reset or timeout resulting
	in a bus reset occurred in the middle of an SCB fetch.

	Don't attempt to perform ULTRA transfers on ultra capable
	adapters missing the external precision resistor required
	for ultra speeds.  I've never encountered an adapter
	configured this way, but better safe than sorry.

        Handle the case of 5MHz user sync rate set as "0" instead of 0x1c
        in scratch ram.

        If we lookup a period of 0 in our table (async), clear the scsi offset.

aic7xxx.h:
	Adjust for the primary channel being represented as
	a 2 bit integer in the flags member of the ahc softc.

	Cleanup the flags definitions so that comment blocks are
	not cramped.

	Update seeprom definitions to correctly reflect the fact
	that the primary channel is represented as a 2 bit integer.

	Add AHC_ULTRA_DIASABLED softc flag to denote controllers
	missing the external precision resistor.

aic7xxx.reg:
	Add DFCACHETH to the definition of DFSTATUS for completness sake.

	Add SEQ_FLAGS2 which currently only contains the SCB_DMA
	(SCB DMA in progress) flag.

aic7xxx.seq:
	Correct a problem when one lun has a disconnected untagged
	transaction and another lun has disconnected tagged transactions.
	Just because an entry is found in the untagged table doesn't
	mean that it will match.  If the match on the lun fails, cleanup
	the SCB (return it to the disconnected list or free it), and snoop
	for a tag message.  Before this change, we reported an unsolicited
	reselection.  This bug was introduced about a month ago during an
	overly aggressive optimization pass on the reselection code.

	When cleaning up an SCB, we can't just blindly free the SCB.  In
	the paging case, if the SCB came off of the disconnected list, its
	state may never have been updated in host memory.  So, check the
	disconnected bit in SCB_CONTROL and return the SCB to the disconnected
	list if appropriate.

	Manage the SCB_DMA flag of SEQ_FLAGS2.

	More carefully shutdown the S/G dma engine in all cases by using
	a subroutine.  Supposedly not doing this can cause an arbiter hang
	on some ULTRA2 chips.

	Formatting cleanup.

	On some chips, at least the aic7856, the transition from
	MREQPEND to HDONE can take a full 4 clock cycles.  Test
	HDONE one more time to avoid this race.  We only want our
	FIFO hung recovery code to execute when the engine is
	really hung.

aic7xxx_93cx6.c:
	Sync perforce ids.

aic7xxx_freebsd.c:
	Adjust for the primary channel being a 2 bit integer
	rather than a flag for 'B' channel being the primary.

	Namespace cleanup.

	Unpause the sequencer in one error recovery path that
	neglected to do so.  This could have caused us to perform
	a bus reset when a recovery message might have otherwise been
	successful.

aic7xxx_freebsd.h:
	Use AHC_PCI_CONFIG for controlling compilation of PCI
	support consistently throughout the driver.

	Move ahc_power_state_change() to OSM.

aic7xxx_inline.h
	Namespace cleanup.

	Adjust our interrupt handler so it will work in the edge
	interrupt case.  We must process all interrupt sources
	when the interrupt fires or risk not ever getting an
	interrupt again.  This involves marking the fact
	that we are relying on an edge interrupt in ahc->flags
	and checking for this condition in addition to the
	AHC_ALL_INTERRUPTS flag.  This fixes hangs on the
	284X and any other aic7770 installation where level
	interrupts are not available.

aic7xxx_pci.c:
	Move the powerstate manipulation code into the OSM.  Several
	OSes now provide this functionality natively.

	Take another shot at using the data stored in scratch ram
	if the SCB2 signature is correct and no SEEPROM data is
	available.  In the past this failed if external SCB ram
	was configured because the memory port was locked.  We
	now release the memory port prior to testing the values
	in SCB2 and re-acquire it prior to doing termination control.

	Adjust for new 2 bit primary channel setting.

	Trust the STPWLEVEL setting on v 3.X BIOSes too.

	Configure any 785X ID in the same fashion and assume
	that any device with a rev id of 1 or higher has the
	PCI 2.1 retry bug.
2001-03-11 06:34:17 +00:00
Justin T. Gibbs
64a3876fef Update Copyright notices for new year. (should have been in last commit). 2001-01-27 20:54:24 +00:00
Justin T. Gibbs
a5847d5c27 ahc_eisa.c:
Initialize rid to 0.  This doesn't seem to make any difference
	(the driver doesn't care what rid it gets and no-one seems to
	check rid's value), but follows standard conventions.

	Pass in our device_t to ahc_alloc().  We now use device_T
	softc storage, so passing NULL results in a panic.

	Set the unit number in our softc so that the driver core
	can retrieve it.

ahc_pci.c:
	Set the unit number in our softc so that the driver core
	can retrieve it.

aic7770.c:
	Insert our softc into the list of softcs when initialization
	is successful.

aic7xxx.c:
	Remove a workaround for an aic7895 bug we will never trigger.

	Add additional diagnostic info to ahc_dump_card_state().

	Always panic the system if a sequencer assertion fails.

	AHC_SCB_BTT is a "flag" not a "feature".  Check the right
	field in the softc.

	Replace a hard coded number with a constant.

	Guard against looping forever in ahc_pause_and_flushwork().
	A hot eject or card failure may make the intstat register
	return 0xFF, so limit the number of interrupts we'll process.

	Correct the code in ahc_search_qinfifo() that guarantees that
	the sequencer will see an abort collision if the qinfifo is
	modified when a DMA is in progress.  We now do this fixup
	after modifying the queue.  This guarantees that the HSCB
	we place at the head of the queue is not the same as the
	old head.  Using "next hscb" (guaranteed not to be the
	same as the first SCB) before clearing the queue could free
	up the original head hscb to be used during a remove operation
	placing it again at the head of the qinfifo.

aic7xxx.h:
	Reduce the maximum number of outstanding commands to 253 from
	254.  To handle our output queue correctly on machines that only
	support 32bit stores, we must clear the array 4 bytes at a
	time.  To avoid colliding with a DMA write from the sequencer,
	we must be sure that 4 slots are empty when we write to clear
	the queue.  This reduces us to 253 SCBs: 1 that just completed
	and the known three additional empty slots in the queue that
	preceed it.  Yahoo was able to force this race on one of their
	systems.  Interrupts were disabled for such a time that the
	entire output queue was filled (254 entries complete without
	any processing), and our 32bit write to clear the status clobbered
	one entry.

	Add a feature tag for devices that are removable.

aic7xxx.reg:
	Never use the sequencer interrupt value of 0xF0.  We need
	to guanrantee that an INTSTAT value of 0xFF can only occur
	during card failure or a hot-eject.

	Align the busy targets table with the begining of scratch
	space.  This seems to appease a chip bug in the aic7895.

aic7xxx.seq:
	Be sure to disable select-out after a bus free event that occurs
	early in a selection.  If we don't disable select-out, we will
	believe that it is enabled even though a new selection will never
	occur.

	Move the clearing of SELDI to just before a jump.  This appeases
	another chip bug of the aic7895.

	Make the target mode command loop a bit more efficient.

	AHC_SCB_BTT is a "flag" not a "feature".  Check the right
	field in the softc.

	Properly cleanup the last SCB we tested against should we
	fail to properly find an SCB for a reselection.

	Add some additional sequencer debugging code.

aic7xxx_freebsd.c:
	Limit the driver to 253 outstanding commands per adapter.

	Guard against overflow in timeout handling.

aic7xxx_inline.h:
	AHC_SCB_BTT is a "flag" not a "feature".  Check the right
	field in the softc.

aic7xxx_pci.c:
	Set the removable feature for the apa1480 cardbus and the 29160C
	Compact PCI card.

	Don't report high byte termination information for narrow cards.

	Use a PCI read rather than a questionable delay when fetching/setting
	termination settings.
2001-01-22 21:03:48 +00:00
Justin T. Gibbs
56a7c4a852 ahc_eisa.c:
ahc_pci.c:
		Add detach support.

		Make use of soft allocated on our behalf by newbus.

		For PCI devices, disable the mapping type we aren't
		using for extra protection from rogue code.

	aic7xxx_93cx6.c:
	aic7xxx_93cx6.h:
		Sync perforce IDs.

	aic7xxx_freebsd.c:
		Capture the eventhandle returned by EVENTHANDER_REGISTER
		so we can kill the handler off during detach.

		Use AHC_* constants instead of hard coded numbers in a
		few more places.

		Test PPR option state when deciding to "really" negotiate
		when the CAM_NEGOTIATE flag is passed in a CCB.

		Make use of core "ahc_pause_and_flushwork" routine in our
		timeout handler rather than re-inventing this code.

		Cleanup all of our resources (really!) in ahc_platform_free().
		We should be all set to become a module now.

		Implement the core ahc_detach() routine shared by all of
		the FreeBSD front-ends.

	aic7xxx_freebsd.h:
		Softc storage for our event handler.

		Null implementation for the ahc_platform_flushwork() OSM
		callback.  FreeBSD doesn't need this as XPT callbacks are
		safe from all contexts and are done directly in ahc_done().

	aic7xxx_inline.h:
		Implement new lazy interrupt scheme.  To avoid an extra
		PCI bus read, we first check our completion queues to
		see if any work has completed.  If work is available, we
		assume that this is the source of the interrupt and skip
		reading INTSTAT.  Any remaining interrupt status will be
		cleared by a second call to the interrupt handler should
		the interrupt line still be asserted.  This drops the
		interrupt handler down to a single PCI bus read in the
		common case of I/O completion.  This is the same overhead
		as in the not so distant past, but the extra sanity of
		perforning a PCI read after clearing the command complete
		interrupt and before running the completion queue to avoid
		missing command complete interrupts added a cycle.

	aic7xxx.c:
		During initialization, be sure to initialize all scratch
		ram locations before they are read to avoid parity errors.
		In this case, we use a new function, ahc_unbusy_tcl() to
		initialize the scratch ram busy target table.

		Replace instances of ahc_index_busy_tcl() used to unbusy
		a tcl without looking at the old value with ahc_unbusy_tcl().

		Modify ahc_sent_msg so that it can find single byte messages.
		ahc_sent_msg is now used to determine if a transfer negotiation
		attempt resulted in a bus free.

		Be more careful in filtering out only the SCSI interrupts
		of interest in ahc_handle_scsiint.

		Rearrange interrupt clearing code to ensure that at least
		one PCI transaction occurrs after hitting CLRSINT1 and
		writting to CLRINT.  CLRSINT1 writes take a bit to
		take effect, and the re-arrangement provides sufficient
		delay to ensure the write to CLRINT is effective.  The
		old code might report a spurious interrupt on some "fast"
		chipsets.

		export ahc-update_target_msg_request for use by OSM code.

		If a target does not respond to our ATN request, clear
		it once we move to a non-message phase.  This avoids
		sending a MSG_NOOP in some later message out phase.

		Use max lun and max target constants instead of
		hard-coded values.

		Use softc storage built into our device_t under FreeBSD.

		Fix a bug in ahc_free() that caused us to delete
		resources that were not allocated.

		Clean up any tstate/lstate info in ahc_free().

		Clear the powerdown state in ahc_reset() so that
		registers can be accessed.

		Add a preliminary function for pausing the chip and
		processing any posted work.

		Add a preliminary suspend and resume functions.

	aic7xxx.h:
		Limit the number of supported luns to 64.  We don't
		support information unit transfers, so this is the
		maximum that makes sense for these chips.

		Add a new flag AHC_ALL_INTERRUPTS that forces the
		processing of all interrupt state in a single invokation
		of ahc_intr().  When the flag is not set, we use the
		lazy interrupt handling scheme.

		Add data structures to store controller state while
		we are suspended.

		Use constants instead of hard coded values where appropriate.

		Correct some harmless "unsigned/signed" conflicts.

	aic7xxx.seq:
		Only perform the SCSIBUSL fix on ULTRA2 or newer controllers.
		Older controllers seem to be confused by this.

		In target mode, ignore PHASEMIS during data phases.
		This bit seems to be flakey on U160 controllers acting
		in target mode.

	aic7xxx_pci.c:
		Add support for the 29160C CPCI adapter.

		Add definitions for subvendor ID information
		available for devices with the "9005" vendor id.
		We currently use this information to determine
		if a multi-function device doesn't have the second
		channel hooked up on a board.

		Add rudimentary power mode code so we can put the
		controller into the D0 state.  In the future this
		will be an OSM callback so that in FreeBSD we don't
		duplicate functionality provided by the PCI code.
		The powerstate code was added after I'd completed
		my regression tests on this code.

		Only capture "left over BIOS state" if the POWRDN
		setting is not set in HCNTRL.

		In target mode, don't bother sending incremental
		CRC data.
2000-12-20 01:11:37 +00:00
Justin T. Gibbs
c498406d58 Add Perforce RCSIDs for easy revision correlation to my local tree.
ahc_pci.c:
	Bring back the AHC_ALLOW_MEMIO option at least until the
	memory mapped I/O problem on the SuperMicro 370DR3 is
	better understood.

aic7xxx.c:
	If we see a spurious SCSI interrupt, attempt to clear it and
	continue by unpausing the sequencer.

	Change the interface to ahc_send_async().  Some async messages
	need to be broadcast to all the luns of a target or all the
	targets of a bus.  This is easier to achieve by passing explicit
	channel, target, and lun parameters instead of attempting to
	construct a device info struct to match.

	Filter the sync parameters for the PPR message in exactly the
	same way we do for an old fashioned SDTR message.

	Correct some typos and correct a panic message.

	Handle rejected PPR messages.

	In ahc_handle_msg_reject(), let ahc_build_transfer_msg() build
	any additional transfer messages instead of doing this inline.

aic7xxx.h:
	Increase the size of both msgout_buf and msgin_buf to
	better accomodate PPR messages.

aic7xxx_freebsd.c:
	Update for change in ahc_send_async() parameters.

aic7xxx_freebsd.h
	Update for change in ahc_send_async() parameters.

	Honor AHC_ALLOW_MEMIO.

aic7xxx_pci.c:
	Check the error register before going into full blown PCI
	interrupt handling.  This avoids a few costly PCI configuration
	space reads when we run our PCI interrupt handler because another
	device sharing our interrupt line is more active than we are.

	Also unpause the sequencer after processing a PCI interrupt.
2000-09-22 22:18:05 +00:00
Justin T. Gibbs
717d424718 Move aicasm to its own subdirectory.
Separate our platform independent hooks from core driver functionality
shared between platforms (FreeBSD and Linux at this time).

Add sequencer workarounds for several chip->chipset interactions.

Correct external SCB corruption problem on aic7895 based cards (3940AUW).

Lots of cleanups resulting from the port to another OS.
2000-09-16 20:02:28 +00:00
Bill Paul
8ebe5155fa *smack* #if 0, not #ifdef 0. 2000-08-04 18:17:45 +00:00
Bill Paul
624539bb38 The check_extport() function appears to have some new code in it that checks
the scratch RAM for data normally found in the SEEPROM (presumably in the
event that the SEEPROM is unavailable or can't be read). This code causes
a spontaneous reboot on monster.osd.bsdi.com, which has an embedded aic7880
controller. The problem appears to happen either when it writes to the
SCBPTR port and then reads from the SCB_CONTROL port. Somewhere during
the inb/outb operations, the system has a heart attack and restarts.

This code looks very suspicious, particularly since it has unconditionalized
debug mesages such as "Got here!" and "And it even worked!". With this
block #ifdef'ed out, the machine boots and runs properly. I stronly suggest
that it stay #ifdef'ed out until it's properly tested.
2000-08-04 18:09:56 +00:00
Justin T. Gibbs
957790c3e6 ahc_pci.c:
Disable "cache line streaming" for aic7890/91 Rev A chips.  I
	have never seen these chips fail using this feature, but
	some of Adaptec's regression tests have.

	Explicitly set "cache line streaming" to on for aic7896/97
	chips.  This was happening before, but this documents the
	fact that these chips will not function correctly without
	CACHETHEEN set.

aic7xxx.h:
	Add new bug types.

	Fix a typo in a comment.

aic7xxx.reg:
	Add a definition for the SHVALID bit in SSTAT3 for Ultra2/3
	chips.  This bit inicates whether the bottom most (current)
	element in the S/G fifo has exhausted its data count.

aic7xxx.seq:
	Be more careful in how we turn off the secondary DMA channel.
	Being less careful may hang the PCI bus arbitor that negotiates
	between the two DMA engines.

	Remove an unecessary and incorrect flag set operation in
	the overrun case.

	On Ultra2/3 controllers, clear the dma FIFO before starting
	to handle an overrun.  We don't want any residual bytes from
	the beginning of the overrun to cause the code that shuts
	down the DMA engine from hanging because the FIFO is not
	(and never will be) empty.

	If the data fifo is empty by the time we notice that a
	read transaction has completed, there is no need to
	hit the flush bit on aic7890/91 hardware that will not
	perform an auto-flush.  Skip some cycles by short circuiting
	the manual flush code in this case.

	When transitioning out of data phase, make sure that we
	have the next S/G element loaded for the following
	reconnect if there is more work to do.  The code
	would do this in most cases before, but there was
	a small window where the current S/G element could
	be exhausted before our fetch of the next S/G element
	completed.  Since the S/G fetch is already initiated
	at this point, it makes sense to just wait for the
	segment to arrive instead of incuring even more latency
	by canceling the fetch and initiating it later.

	Fast path the end of data phase handling for the last
	S/G segment.   In the general case, we might have
	worked ahead a bit by stuffing the S/G FIFO with
	additional segments.  If we stop before using them
	all, we need to fixup our location in the S/G stream.
	Since we can't work past the last S/G segment, no
	fixups are ever required if we stop somewhere in
	that final segment.

	Fix a little buglet in the target mode dma bug handler.
	We were employing the workaround in all cases instead
	of only for the chips that require it.

	Fix the cause of SCB timeouts and possible "lost data"
	during read operations on the aic7890.  When sending
	a data on any Ultra2/3 controller, the final segment
	must be marked as such so the FIFO will be flushed and
	cleaned up correctly when the transfer is ended.  We
	failed to do this for the CDB transfer and so, if
	the target immediately transfered from command to data
	phase without an intervening disconnection, the first
	segment transferred would be any residual bytes from
	the cdb transfer.  The Ultra160 controllers for some
	reason were not affected by this problem.

Many Thanks to Tor Egge for bringing the aic7890 problem
to my attention, providing analysis, as well as a mechanism
to reproduce the problem.
2000-07-27 23:17:52 +00:00
Justin T. Gibbs
aa6dfd9d3d o Convert to <inttypes.h> style fixed sized types to facilitate porting to
other systems.

 o Normalize copyright text.

 o Clean up probe code function interfaces by passing around a single
   structure of common arguments instead of passing "too many" args
   in each function call.

 o Add support for the AAA-131 as a SCSI adapter.

 o Add support for the AHA-4944 courtesy of "Matthew N. Dodd" <winter@jurai.net

 o Correct manual termination support for PCI cards.  The bit definitions
   for manual termination control in the SEEPROM were incorrect.

 o Add support for extracting NVRAM information from SCB 2 for BIOSen
   that use this mechanism to pass this data to OS drivers.

 o Properly set the STPWLEVEL bit in PCI config space based on the
   setting in an SEEPROM.

 o Go back to useing 32byte SCBs for all controllers.  The current
   firmware allows us to embed 12byte cdbs on all controllers in
   a 32byte SCB, and larger cdbs are rarely used, so it is a
   better use of this space to offer more SCBs (32).

 o Add support for U160 transfers.

 o Add an idle loop executed during data transfers that prefetches
   S/G segments on controllers that have a secondary DMA engine
   (aic789X).

 o Improve the performance of reselections by avoiding an extra
   one byte DMA in the case of an SCB lookup miss for the reselecting
   target.  We now keep a 16byte "untagged target" array on the card
   for dealing with untagged reselections.  If the controller has
   external SCB ram and can support 64byte SCBs, then we use an
   "untagged target/lun" array to maximize concurrency.  Without
   external SCB ram, the controller is limited to one untagged
   transaction per target, auto-request sense operations excluded.

 o Correct the setup of the STPWEN bit in SXFRCTL1.  This control
   line is tri-stated until set to one, so set it to one and then
   set it to the desired value.

 o Add tagged queuing support to our target role implementation.

 o Handle the common cases of the ignore wide residue message
   in firmware.

 o Add preliminary support for 39bit addressing.

 o Add support for assembling on big-endian machines.  Big-endian
   support is not complete in the driver.

 o Correctly remove SCBs in the waiting for selection queue when
   freezing a device queue.

 o Now that we understand more about the autoflush bug on the
   aic7890, only use the workaround on devices that need it.

 o Add a workaround for the "aic7890 hangs the system when you
   attempt to pause it" problem.  We can now pause the aic7890
   safely regardless of what instruction it is executing.
2000-07-18 20:12:14 +00:00
Peter Wemm
9e5c01ffe6 Use the correct register names, not the FreeBSD 2.2 compatability ones. 2000-05-28 15:47:00 +00:00
Justin T. Gibbs
c4b5781296 KNR -> ANSI function definition in two places. This matches the rest of
the code in this driver.
2000-03-18 22:15:00 +00:00
Justin T. Gibbs
945111e5a7 Remove a diagnostic printf.
Noticed by:	 imp@FreeBSD.org
2000-02-16 18:41:00 +00:00
Justin T. Gibbs
1907f932b8 Fix parity error detection logic for aic7880 and aic7895 chips during
the probe of external SRAM.

Approved by: jkh@FreeBSD.org
2000-02-09 21:00:22 +00:00
Justin T. Gibbs
dbf94fd693 Avoid setting DPARCKEN until I can figure out why it causes
spurious parity errors on some controllers.
2000-01-10 01:47:51 +00:00
Justin T. Gibbs
1a24969d60 Turn on parity error reporting before configuring external sram. This
makes it a little easier to notice that parity checking an 8bit sram
isn't working.

Turn on scb and internal data-path parity checking for all pci chips types.
We were only doing this for ultra2 chips.

After clearing the parity interrupt status, clear the BRKADRINT.  This
avoids seeing a bogus BRKADRINT interrupt after external SCB probing
once normal interrupts are enabled.
2000-01-08 05:31:38 +00:00
Justin T. Gibbs
c971c124a1 Really enable external SCB ram on Ultra2 capable controllers.
Don't even bother to look for SCB ram on controllers < aic7870.

Clear any parity errors generated by looking at external SCB ram.
2000-01-08 00:32:08 +00:00
Justin T. Gibbs
77dd846834 Add detection logic for the U160 family of adaptec controllers. These
controllers will run at U2 speeds until I can complete the U160 support
for this driver.

Correct a termination buglet for the 2940UW-Pro.

Be more paranoid in how we probe and enable external ram, fast external
ram timing and external ram parity checking.  We should now work on
20ns and 8bit SRAM parts.

Perform initial setup for the DT feature on cards that support it.

Factorize and clean up code.  Use tables where it makes sense, etc.

Add some delays in dealing with the board control logic.  I've never
seen this code fail, but with the ever increasing speed of processors,
its better to insert deterministic delays just to be safe.  This stuff
is only touched during probe and attach, so the extra delay is of no
concern.
2000-01-07 22:53:37 +00:00
Justin T. Gibbs
e0b0c6aad5 When booting verbose, indicate if we are using manual termination
settings for U2 cards.

Don't assume that all aic7859 cards are 2930CUs.
1999-12-12 04:54:14 +00:00
Justin T. Gibbs
820379186b Simplify my license.
Don't arbitrarily limit the initiator ID of the card to something <= 7.

Fix a bug in the checksum code that would incorrectly prevent a valid
checksum of zero. (cp)

Don't touch rely on seeprom data when configuring termination.  We may
not have seeprom data. (cp)

Treat all ULTRA2 capable adapters the same way when reading or writing
the BRDCTL register.  We previously only did this correctly for aic7890/91
chips.  This should correct some problems with termination settings on
aic7896/97 adapters. (cp)

Changes marked with "(cp)"
Pointed out by:	Chuck Paterson <cp@bsdi.com>
1999-12-06 18:29:03 +00:00
Kenneth D. Merry
20d39afec3 Get rid of a stray printf on boot. (BRDCTL = ...)
Approved by:	gibbs
1999-09-13 16:32:34 +00:00
Justin T. Gibbs
5bdd92770e Add support for the aic7859 which is found on the 2930CU.
Break out the detection logic for the aic7855 and properly report
these chips as 7855s instead of 7850s.

The 2940AU_CN is an aic7860 based card, not aic7860.

Not setting CACHETHEN turned out to be a bad idea.  It can cause
spurious corruption under heavy PCI load with multiple masters.
1999-08-30 16:11:46 +00:00
Peter Wemm
c3aac50f28 $Id$ -> $FreeBSD$ 1999-08-28 01:08:13 +00:00
Justin T. Gibbs
99cfa26a69 Differentiate between aic7895C chips and their earlier brethren
via the PCI revid register.
1999-08-16 22:50:37 +00:00
Justin T. Gibbs
7debf5e75e Fix a long standing bug in the auto-termination control settings for
the aic7890/91/96/97 cards.  This could cause the system to go into
a long retry/recovery loop during probe.

Fix the alignment argument to bus_dma_tag_create().

Don't set the CACHETHEN bit in dscommand0 for Ultra2 controllers
until we know more about its behavior.  The description for this
bit makes it sound like it could cause problems with certain
PCI chipsets.
1999-08-16 02:33:46 +00:00
Peter Wemm
9929d2a045 Eliminate a bunch of #include "pci.h" and #if NPCI > 0 around entire
files.  config will leave the whole file out if configured to do so.
1999-07-03 20:17:08 +00:00
Justin T. Gibbs
51064aaaf8 Ignore subvendor and subdevice ids for all ai7880 parts. These chips
only support 'mirroring' the vendor and device ids, so we don't
lose any information.  Certain revisions of the aic7880 will not
perform the mirroring so to match all possiblities would double
the number of table entries.  This change also allows us to match
things like the 2944B which I missed in the original table.
1999-05-26 16:59:17 +00:00
Justin T. Gibbs
f40c8d7155 All cards using aic789X chips use the new eeprom format.
Corrects bogus negotiation values on aic7890 based controllers.

PR: 11872
1999-05-25 20:12:32 +00:00
Justin T. Gibbs
923dc21bfe Add a masking scheme to allow for detection of unknown cards using a
chip we think we understand.

Correct identification entry for the AHA2950U2.
1999-05-17 21:53:09 +00:00
Justin T. Gibbs
168d6886b8 Use a lookup table for device matching instead of a switch on a 64bit
value.  EGCS generates poor code for sparse switch statements on 64bit
values.

Requested by: bde
1999-05-14 17:38:07 +00:00
Justin T. Gibbs
f3da2c5d80 Take the subvendor and subdevice ids into account during device probe.
Sync up device Ids with the master Adaptec list.

Add probe support for the 2940 Pro although it isn't obvious that
all of the termination support is correct for this adapter yet.
1999-05-14 05:09:24 +00:00
Doug Rabson
566643e39e Move the declaration of the interrupt type from the driver structure
to the BUS_SETUP_INTR call.
1999-05-08 21:59:43 +00:00
Justin T. Gibbs
1d28309371 ahc_pci.c:
Convert to new bus and bus dma.
	Use latest PCI API.

bt_pci.c:
	Fix a few bugs in how resourses are released left over from
	when this driver was converted to new bus.
1999-04-23 23:30:22 +00:00
Justin T. Gibbs
73c9c6dd62 Add support for the 3950U2B controller.
Recognize aic7895 controllers that have been "acquired" by a RAIDPort
card as normal aic7895s.

Recognize the aic7815 Raid Parity/Memory controller chip and notify
the user that it's RAID functionality will be ignored.
1999-03-23 07:26:41 +00:00
Justin T. Gibbs
b08ce6a386 Add untested code to support the aha2930U2W.
Modify to deal with changes in the storage of user negotiation settings.
1999-03-05 23:28:36 +00:00
Justin T. Gibbs
957fea92f0 Set the ultra enable bits in the adaptor's scratch ram area only after
we finish modifying our in kernel version during seeprom configuration.
1999-02-11 07:12:16 +00:00
Justin T. Gibbs
41faa7d374 Pull in new ccb_hdr list types. 1998-12-15 08:24:45 +00:00
Matthew Dillon
35f069d08b pci_device pd_probe function changed from returning char * to returning
const char *.  Originally I was going to add casts from const char * to
    char * in some of the pci device drivers, but the reality is that the
    pci device probes return constant quoted strings.
1998-12-14 05:47:29 +00:00
Archie Cobbs
f1d19042b0 The "easy" fixes for compiling the kernel -Wunused: remove unreferenced static
and local variables, goto labels, and functions declared but not defined.
1998-12-07 21:58:50 +00:00
Justin T. Gibbs
6405ed07d7 ahc_pci.c:
Disable DPARCKEN in the DSCOMMAND0 register on the aic7890/91/96/97.
	Parity checking is broken for some chip/MB combinations and this
	is the work around recommended by Adaptec.

dpt_pci.c:
	Remove a superflous '{' that prevented DPT_ALLOW_MEMIO from working.

pcireg.h:
	Add a definition for Parity Error Reponse bit in the PCI Space
	command register.
1998-10-07 03:40:51 +00:00
Justin T. Gibbs
4530878e33 Move to new name, convert to CAM, add support for new chips, and
correct lots of eeprom/auto-termination bugs.
1998-09-15 07:25:33 +00:00