Commit Graph

1367 Commits

Author SHA1 Message Date
alc
309c5ab06f Add a new sysctl for reporting all of the supported page sizes.
Reviewed by:	jhb
MFC after:	3 weeks
2009-09-18 17:04:57 +00:00
nwhitehorn
9b112771c1 Add a few SCSI controllers to GENERIC that can be found on Powermacs.
This allows installation onto SCSI disks as shipped, for example,
with the Powermac G3.

PR:		powerpc/138543
Obtained from:	sparc64
MFC after:	3 days
2009-09-10 21:25:05 +00:00
phk
e645b495ed Get rid of the _NO_NAMESPACE_POLLUTION kludge by creating an
architecture specific include file containing the _ALIGN*
stuff which <sys/socket.h> needs.
2009-09-08 20:45:40 +00:00
nwhitehorn
aead28d158 Remove some debugging (KTR_VERBOSE) that crept into ppc GENERIC long ago
and is present on no other architectures by default.

MFC after:	4 days
2009-09-08 20:12:26 +00:00
attilio
e85ca71aad * Completely Remove the option STOP_NMI from the kernel. This option
has proven to have a good effect when entering KDB by using a NMI,
but it completely violates all the good rules about interrupts
disabled while holding a spinlock in other occasions.  This can be the
cause of deadlocks on events where a normal IPI_STOP is expected.
* Adds an new IPI called IPI_STOP_HARD on all the supported architectures.
This IPI is responsible for sending a stop message among CPUs using a
privileged channel when disponible. In other cases it just does match a
normal IPI_STOP.
Right now the IPI_STOP_HARD functionality uses a NMI on ia32 and amd64
architectures, while on the other has a normal IPI_STOP effect. It is
responsibility of maintainers to eventually implement an hard stop
when necessary and possible.
* Use the new IPI facility in order to implement a new userend SMP kernel
function called stop_cpus_hard(). That is specular to stop_cpu() but
it does use the privileged channel for the stopping facility.
* Let KDB use the newly introduced function stop_cpus_hard() and leave
stop_cpus() for all the other cases
* Disable interrupts on CPU0 when starting the process of APs suspension.
* Style cleanup and comments adding

This patch should fix the reboot/shutdown deadlocks many users are
constantly reporting on mailing lists.

Please don't forget to update your config file with the STOP_NMI
option removal

Reviewed by:	jhb
Tested by:	pho, bz, rink
Approved by:	re (kib)
2009-08-13 17:09:45 +00:00
jhb
44220d7e1e Add a new type of VM object: OBJT_SG. An OBJT_SG object is very similar to
a device pager (OBJT_DEVICE) object in that it uses fictitious pages to
provide aliases to other memory addresses.  The primary difference is that
it uses an sglist(9) to determine the physical addresses for a given offset
into the object instead of invoking the d_mmap() method in a device driver.

Reviewed by:	alc
Approved by:	re (kensmith)
MFC after:	2 weeks
2009-07-24 13:50:29 +00:00
raj
b89a897a7d Do not use OCP85XX_LBC_OFF twice when accessing LBC registers on MPC85XX.
It turns LBC control registers were not programmed correctly on MPC85XX. We
were accessing bogus addresses as the base offset (OCP85XX_LBC_OFF) was
erroneously added during offset calculations.  Effectively the state of LBC
control registers was not altered by the kernel initialization code, but
everything worked as long as we coincided to use the same settings (LBC decode
windows) as firmware has initialized.

Submitted by:	Lukasz Wojcik
Reviewed by:	marcel
Approved by:	re (kensmith)
Obtained from:	Semihalf
2009-07-21 08:38:45 +00:00
alc
ea60573817 Add support to the virtual memory system for configuring machine-
dependent memory attributes:

Rename vm_cache_mode_t to vm_memattr_t.  The new name reflects the
fact that there are machine-dependent memory attributes that have
nothing to do with controlling the cache's behavior.

Introduce vm_object_set_memattr() for setting the default memory
attributes that will be given to an object's pages.

Introduce and use pmap_page_{get,set}_memattr() for getting and
setting a page's machine-dependent memory attributes.  Add full
support for these functions on amd64 and i386 and stubs for them on
the other architectures.  The function pmap_page_set_memattr() is also
responsible for any other machine-dependent aspects of changing a
page's memory attributes, such as flushing the cache or updating the
direct map.  The uses include kmem_alloc_contig(), vm_page_alloc(),
and the device pager:

  kmem_alloc_contig() can now be used to allocate kernel memory with
  non-default memory attributes on amd64 and i386.

  vm_page_alloc() and the device pager will set the memory attributes
  for the real or fictitious page according to the object's default
  memory attributes.

Update the various pmap functions on amd64 and i386 that map pages to
incorporate each page's memory attributes in the mapping.

Notes: (1) Inherent to this design are safety features that prevent
the specification of inconsistent memory attributes by different
mappings on amd64 and i386.  In addition, the device pager provides a
warning when a device driver creates a fictitious page with memory
attributes that are inconsistent with the real page that the
fictitious page is an alias for. (2) Storing the machine-dependent
memory attributes for amd64 and i386 as a dedicated "int" in "struct
md_page" represents a compromise between space efficiency and the ease
of MFCing these changes to RELENG_7.

In collaboration with: jhb

Approved by:	re (kib)
2009-07-12 23:31:20 +00:00
nwhitehorn
04a1b965bd Increase the size of the page table on 64-bit PowerPC machines as a
bandaid to prevent exhaustion of the primary and secondary hash groups
in the event of extreme stress on the PMAP layer (e.g. a forkbomb). This
wastes memory, and should be revised to properly handle PTEG spills instead.

Suggested by:	grehan
Approved by:	re (kensmith)
2009-07-12 04:07:52 +00:00
sam
c67dff7aca Cleanup ALIGNED_POINTER:
o add to platforms where it was missing (arm, i386, powerpc, sparc64, sun4v)
o define as "1" on amd64 and i386 where there is no restriction
o make the type returned consistent with ALIGN
o remove _ALIGNED_POINTER
o make associated comments consistent

Reviewed by:	bde, imp, marcel
Approved by:	re (kensmith)
2009-07-05 17:45:48 +00:00
ed
f11b84cef6 Enable POSIX semaphores on all non-embedded architectures by default.
More applications (including Firefox) seem to depend on this nowadays,
so not having this enabled by default is a bad idea.

Proposed by:	miwi
Patch by:	Florian Smeets <flo kasimir com>
Approved by:	re (kib)
2009-07-02 18:24:37 +00:00
alc
1ce12d013e Correct the #endif comment.
Noticed by:	jmallett
Approved by:	re (kib)
2009-06-26 16:22:24 +00:00
alc
91cafd48b1 This change is the next step in implementing the cache control functionality
required by video card drivers.  Specifically, this change introduces
vm_cache_mode_t with an appropriate VM_CACHE_DEFAULT definition on all
architectures.  In addition, this changes adds a vm_cache_mode_t parameter
to kmem_alloc_contig() and vm_phys_alloc_contig().  These will be the
interfaces for allocating mapped kernel memory and physical memory,
respectively, with non-default cache modes.

In collaboration with:	jhb
2009-06-26 04:47:43 +00:00
raj
078b9535f0 Include SMP support in the MPC85XX kernel by default. 2009-06-25 10:07:21 +00:00
jeff
1095cbed62 - Add the right includes to use kmem_alloc(). This was broken by my
DPCPU commit.
Reported by:	bz
2009-06-25 00:14:27 +00:00
raj
cb09752da0 More precise description of the DS1553 driver.
Pointed out by:	stas
2009-06-24 15:48:20 +00:00
jeff
5bc3a65e40 Implement a facility for dynamic per-cpu variables.
- Modules and kernel code alike may use DPCPU_DEFINE(),
   DPCPU_GET(), DPCPU_SET(), etc. akin to the statically defined
   PCPU_*.  Requires only one extra instruction more than PCPU_* and is
   virtually the same as __thread for builtin and much faster for shared
   objects.  DPCPU variables can be initialized when defined.
 - Modules are supported by relocating the module's per-cpu linker set
   over space reserved in the kernel.  Modules may fail to load if there
   is insufficient space available.
 - Track space available for modules with a one-off extent allocator.
   Free may block for memory to allocate space for an extent.

Reviewed by:    jhb, rwatson, kan, sam, grehan, marius, marcel, stas
2009-06-23 22:42:39 +00:00
nwhitehorn
f711522f3c Add cpufreq support on the PowerPC G5, along with a skeleton SMU driver
in order to slew CPU voltage during frequency changes. The OpenBSD SMU
driver was an extremely helpful reference for this.
2009-06-23 04:28:32 +00:00
nwhitehorn
abe79136cc Fix copy/paste typo in last revision. PMC0 control should be shifted 8
bits, not 6, on the PPC 970.
2009-06-23 04:02:36 +00:00
raj
505fac5d7f DS1553 RTC module driver. On the MPC8555CDS system it hangs off of the LBC bus.
Obtained from:	Semihalf
2009-06-22 15:48:47 +00:00
raj
7309749fbc Integrated I2C controller driver (found in MPC85xx and other SOC parts).
Obtained from:	Freescale, Semihalf
2009-06-22 15:34:32 +00:00
nwhitehorn
9693648e9f Teach cpu_est_clockrate() about the G5's slightly different PMC. This
allows the boot messages to include the CPU speed and makes possible
the forthcoming cpufreq support for the PPC 970.
2009-06-17 16:34:40 +00:00
alc
46cf688d11 Correct the method of waking the page daemon when the number of allocated
pv entries surpasses the high water mark.  The problem was that the page
daemon would only be awakened the first time that the high water mark was
surpassed.  (The variable "pagedaemon_waken" is a non-working vestige of
FreeBSD 4.x, in which it was external and reset by the page daemon whenever
it ran.  This reset allowed subsequent wakeups by the pv entry allocator.)
2009-06-13 18:35:29 +00:00
raj
1605e27e02 Fix Book-E/MPC85XX build. Some prototypes were wrong and got revealed with
the recent kobj signature checking.
2009-06-13 08:57:04 +00:00
avg
2ae00ba3ff strict kobj signatures: fix adb_hb_controller_poll impl in powermac
the method return u_int, not void

Reviewed by:	imp, current@
Approved by:	jhb (mentor)
2009-06-11 17:16:04 +00:00
avg
7e0d744efe strict kobj signatures: some ofw_setprop fixes
propname parameter is const

Reviewed by:	imp, current@
Approved by:	jhb (mentor)
2009-06-11 17:15:20 +00:00
imp
cb4bb46e16 Move from using devclass_find_free_unit(ata_devclass, 0) to -1 for the
unit number.  Basically they are the same...
2009-06-10 17:40:18 +00:00
grehan
695df43388 Get the gdb/psim emulator functioning again.
aim/machdep.c:
  - the	RI status register bit needs to be set when	doing the mtmsrd 64-bit
    instruction	test
  - psim doesn't implement the dcbz instruction	so the run-time	cacheline
    test fails.	Set the	cachline size to 32 to avoid infinite loops in
    future calls to __syncicache()

aim/platform_chrp.c:
  - if after iterating through / and a name property of "cpus" still isn't
    found, just	search directly	for '/cpus'.
  - psim doesn't put a "reg" property on it's cpu nodes, so assume 0
    since it is	uniprocessor-only at this point

powerpc/openpic.c
  - the	number of CPUs reported	is 1 too many on psim's	openpic

Reviewed by:	nwhitehorn
MFC after:	1 week (openpic part)
2009-06-10 12:47:54 +00:00
raj
4438ca8fc5 Initial version of the sec(4) driver for the integrated security engine found
in Freescale system-on-chip devices.

The following algorithms and schemes are currently supported:
  - 3DES, AES, DES
  - MD5, SHA1, SHA256, SHA384, SHA512

Reviewed by:	philip
Obtained from:	Freescale, Semihalf
2009-06-06 09:37:55 +00:00
raj
482c6163f8 Provide 64-bit big endian bus space operations for PowerPC. They are required
for the upcoming sec(4) driver.

Submitted by:	Piotr Ziecik
Obtained from:	Semihalf
2009-06-06 09:33:32 +00:00
raj
8a4e071b72 Discover and handle the number of E500 CPUs in run time. 2009-06-05 09:46:00 +00:00
raj
81b8f443e2 Fill PTEs covering kernel code and data.
Without this fix pte_vatopa() was not able to retrieve physical address of
data structures inside kernel, for example EFAULT was reported while acessing
/dev/kmem ('netstat -nr').

Submitted by:	Piotr Ziecik
Obtained from:	Semihalf
2009-06-05 09:09:46 +00:00
rwatson
14f4a9dd42 Remove MAC kernel config files and add "options MAC" to GENERIC, with the
goal of shipping 8.0 with MAC support in the default kernel.  No policies
will be compiled in or enabled by default, but it will now be possible to
load them at boot or runtime without a kernel recompile.

While the framework is not believed to impose measurable overhead when no
policies are loaded (a result of optimization over the past few months in
HEAD), we'll continue to benchmark and optimize as the release approaches.
Please keep an eye out for performance or functionality regressions that
could be a result of this change.

Approved by:	re (kensmith)
Obtained from:	TrustedBSD Project
2009-06-02 18:31:08 +00:00
nwhitehorn
3eefad2beb Provide an analogous sysctl to hw.acpi.acline (dev.pmu.0.acline) to
determine whether the computer is plugged in to mains power.
2009-05-31 10:02:20 +00:00
nwhitehorn
26eb077d03 Introduce support for cpufreq on PowerPC with the dynamic frequency
switching capabilities of the MPC7447A and MPC7448.
2009-05-31 09:01:23 +00:00
marcel
a42ef97c19 Mark the cascaded AT interrupt handler as MP safe to avoid having
it grab Giant. The next step would be to make it a filter.
2009-05-31 01:56:06 +00:00
raj
8a00db9f7f Set PG_WRITEABLE in Book-E pmap_enter[_locked] if it creates a mapping that
permits write access. This is similar to r192671.

Pointed out and reviewed by:	alc
2009-05-26 06:24:50 +00:00
raj
333b42e3d8 Improve style(9), clean up. 2009-05-21 12:05:15 +00:00
raj
84c7ebbafb Initial support for SMP on PowerPC MPC85xx.
Tested with Freescale dual-core MPC8572DS development system.

Obtained from:	Freescale, Semihalf
2009-05-21 11:43:37 +00:00
raj
e0229d3977 Skip interleaved RAM target on MPC85xx during renitialization of the local
access windows. This eliminates hangs on systems which are configured to use
interleaved mode: prior to this fix we were simply cutting ourselves from
access to the main memory in this case.

Obtained from:	Freescale, Semihalf
2009-05-21 11:37:56 +00:00
marcel
8b09116a5a Add cpu_flush_dcache() for use after non-DMA based I/O so that a
possible future I-cache coherency operation can succeed. On ARM
for example the L1 cache can be (is) virtually mapped, which
means that any I/O that uses temporary mappings will not see the
I-cache made coherent. On ia64 a similar behaviour has been
observed. By flushing the D-cache, execution of binaries backed
by md(4) and/or NFS work reliably.
For Book-E (powerpc), execution over NFS exhibits SIGILL once in
a while as well, though cpu_flush_dcache() hasn't been implemented
yet.

Doing an explicit D-cache flush as part of the non-DMA based I/O
read operation eliminates the need to do it as part of the
I-cache coherency operation itself and as such avoids pessimizing
the DMA-based I/O read operations for which D-cache are already
flushed/invalidated. It also allows future optimizations whereby
the bcopy() followed by the D-cache flush can be integrated in a
single operation, which could be implemented using on-chips DMA
engines, by-passing the D-cache altogether.
2009-05-18 18:37:18 +00:00
raj
7b55e64dac Improve style(9) 2009-05-14 16:56:56 +00:00
raj
e648274e7c PowerPC common SMP startup and time base rework.
- make mftb() shared, rewrite in C, provide complementary mttb()
- adjust SMP startup per the above, additional comments, minor naming
  changes
- eliminate redundant TB defines, other minor cosmetics

Reviewed by:	marcel, nwhitehorn
Obtained from:	Freescale, Semihalf
2009-05-14 16:48:25 +00:00
nwhitehorn
dc1ac440de Factor out platform dependent things unrelated to device drivers into a
new platform module. These are probed in early boot, and have the
responsibility of determining the layout of physical memory, determining
the CPU timebase frequency, and handling the zoo of SMP mechanisms
found on PowerPC.

Reviewed by:	marcel, raj
Book-E parts by: raj
2009-05-14 00:34:26 +00:00
kuriyama
9913dad783 - Use "device\t" and "options \t" for consistency. 2009-05-10 00:00:25 +00:00
raj
9d122f9cba Zero PCB during early AIM PowerPC init.
When memory is not zero'ed by firmware, uninitialized PCB can have bogus
contents, which appear as a saved onfault condition, Altivec context to
restore etc. and lead to corruption/crashes. This commit fixes such issues.

Submitted by:	Michal Mazur arg ! semihalf dot com
Tested by:	Andreas Tobler andreast-list ! fgznet dot ch
2009-04-24 08:57:54 +00:00
marcel
01cb4e7961 Add suppport for ISA and ISA interrupts to make the ATA
controller in the VIA southbridge functional in the CDS
(Configurable Development System) for MPC85XX.
The embedded USB controllers look operational but the
interrupt steering is still wrong.
2009-04-24 03:51:11 +00:00
marcel
ae430908a2 Reimplement bs_be_rs_{1|2|4} and bs_le_rs_{1|2|4} by not
calling the inline functions in <machine/pio.h> and do
not add synchronization. Implement bs_gen_barrier() as
eieio and sync.
2009-04-24 03:06:32 +00:00
marcel
f2a1682c40 Remove PTE_FAKE and PTE_ISFAKE(). 2009-04-24 02:55:20 +00:00
marcel
f0ba161c81 Remove PTE_ISFAKE. While here remove code
between "#if 0" and "#endif".
2009-04-24 02:53:38 +00:00