4 Commits

Author SHA1 Message Date
andrew
72392dc5f8 Only work around errata when we are on a part where the erratum applies.
Reviewed by:	gonzo
2013-01-06 00:42:09 +00:00
andrew
93a0b775d9 Document the known values of the RTL release field in the cache is register 2013-01-01 03:48:39 +00:00
gonzo
a381b05232 PL310 driver update:
- Add pl310.disable tunable to disable L2 cache altogether. In
    order to make sure that it's 100% disabled we use cache event
    counters for cache line eviction and read allocate events
    and panic if any of these counters increased. This is purely
    for debugging purpose
- Direct access DEBUG_CTRL and CTRL might be unavailable in
    unsecure mode, so use platform-specific functions for
    these registers
- Replace #if 1 with proper erratum numbers
- Add erratum 753970 workaround
- Remove wait function for atomic operations
- Protect cache operations with spin mutex in order to prevent race condition
- Disable instruction cache prefetch and make sure data cache
    prefetch is enabled in OMAP4-specific intialization
2012-12-31 21:19:44 +00:00
gonzo
032427f3e9 Merging projects/armv6, part 1
Cummulative patch of changes that are not vendor-specific:
	- ARMv6 and ARMv7 architecture support
	- ARM SMP support
	- VFP/Neon support
	- ARM Generic Interrupt Controller driver
	- Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00