Commit Graph

1140 Commits

Author SHA1 Message Date
adrian
d4acb4d1d5 Revert this; it wasn't supposed to be part of this commit. 2012-07-23 03:55:19 +00:00
adrian
c89f08ceb9 Begin separating out the TX DMA setup in preparation for TX EDMA support.
* Introduce TX DMA setup/teardown methods, mirroring what's done in
  the RX path.

  Although the TX DMA descriptor is setup via ath_desc_alloc() /
  ath_desc_free(), there TX status descriptor ring will be allocated
  in this path.

* Remove some of the TX EDMA capability probing from the RX path and
  push it into the new TX EDMA path.
2012-07-23 03:52:18 +00:00
adrian
505896c97a Flesh out a new DMA map for the EDMA TX completion status, as well
as a lock to go with that whole code path.
2012-07-23 02:49:25 +00:00
adrian
f20813da65 Begin modifying the descriptor allocation functions to support a variable
sized TX descriptor.

This is required for the AR93xx EDMA support which requires 128 byte
TX descriptors (which is significantly larger than the earlier
hardware.)
2012-07-23 02:26:33 +00:00
adrian
0ca2458360 Introduce a rate table TLV so rate table statistics consumers
know how to map rix -> rate code.
2012-07-20 02:17:48 +00:00
adrian
4939a38c3f Bump this up to match what the HAL is at now. 2012-07-20 01:41:18 +00:00
adrian
ff4507cc5c Enable the basic node-based rate control statistics via an ioctl(). 2012-07-20 01:36:46 +00:00
adrian
233485e7d2 Add a per-node rate control routine for each rate control module.
For now, the only module implement is 'sample', and that's only partially
implemented.  The main issue here with reusing this structure in userland
is that it uses 'rix' everywhere, which requires the userland code to
have access to the current HAL rate table.

For now, this is a very large work in progress.

Specific details:

* The rate control information is per-node at the moment and wrapped
  in a TLV, to ease parsing and backwards compatibility.
* .. but so I can be slack for now, the userland statistics are just
  a copy of the kernel-land sample node state.
* However, for now use a temporary copy and change the rix entries
  to dot11rate entries to make it slightly easier to eyeball.

Problems:

* The actual rate information table is unfortunately indexed by rix
  and it doesn't contain a rate code.  So the userland side of this
  currently has no way to extract out a mapping.

TODO:

* Add a TLV payload to dump out the rate control table mapping so
  'rix' can be turned into a dot11 / MCS rate.
* .. then remove the temporary copy.
2012-07-20 01:36:02 +00:00
adrian
bfcf6a8af8 Create an ioctl API for fetching the current rate control information. 2012-07-20 01:27:20 +00:00
adrian
be9f867582 Prepare for (re)using this header file in userland.
Remove the inlined code from the header file if it's compiled in userland.
It's not required and it shouldn't be there in the first place.
2012-07-20 00:47:23 +00:00
adrian
0dca43b8b6 Convert the TX path to use the new HAL methods for accessing the
TX descriptor link pointers.

This is required for the AR93xx and later chipsets.

The RX path is slightly different - the legacy RX path directly
accesses ath_desc->ds_link for now, however this isn't at all done
for EDMA (FIFO) RX.

Now, for those performing a little software archeology here:

This is all a bit sub-optimal. "struct ath_desc" is only really relevant
for the pre-AR93xx NICs - where ds_link and ds_data is always in the
same location.

The AR93xx and later NICs have different descriptor layouts altogether.

Now, for AR93xx and later NICs, you should never directly reference
ds_link and ds_data, as:

* the RX descriptors don't have either - the data is _after_ the RX
  descriptor.  They're just one large buffer.  There's also no need for
  a per-descriptor RX buffer size as they're all fixed sizes.

* the TX descriptors have 4 buffer and 4 length fields _and_ a link
  pointer.  Each frame takes up one TX FIFO pointer, but it can contain
  multiple subframes (either multiple frames in a buffer, and/or
  multiple frames in an aggregate/RIFS burst.)

* .. so, when TX frames are queued to a hardware queue, the link
  pointer is ONLY for buffers in that frame/aggregate.  The next frame
  starts in a new FIFO pointer.

* Finally, descriptor completion status is in a different ring.
  I'll write something up about that when its time to do so.

This was inspired by Linux ath9k and the reference driver but is a
reimplementation.

Obtained from:	Linux ath9k, Qualcomm Atheros
2012-07-19 03:51:16 +00:00
adrian
158ed614ca Use HAL_NUM_RX_QUEUES rather than a magic constant. 2012-07-19 03:18:15 +00:00
adrian
770c2e2c10 Break out the TX descriptor link field into HAL methods.
The DMA FIFO chips (AR93xx and later) differ slightly to th elegacy
chips:

* The RX DMA descriptors don't have a ds_link field;
* The TX DMA descriptors have a ds_link field however at a different
  offset.

This is a reimplementation based on what the reference driver and ath9k
does.

A subsequent commit will enable it in the TX and beacon paths.

Obtained from:	Linux ath9k, Qualcomm Atheros
2012-07-19 02:25:14 +00:00
adrian
c486d0bf45 Handle RX Keymiss events.
The AR9003 series NICs implement a separate RX error to signal that a
Keycache miss occured.  The earlier NICs would not set the key index
valid bit.

I'll dig into the difference between "no key index bit set" and "keycache
miss".
2012-07-15 20:51:41 +00:00
adrian
f3c1c1a422 Log the number of handled decsriptors and valid descriptors when
hitting RXEOL.
2012-07-15 20:48:21 +00:00
adrian
f986686460 Fix build breakage when one isn't building with IEEE80211_SUPPORT_SUPERG.
Noticed by:	mav
2012-07-14 12:15:20 +00:00
adrian
5c389e063d Merge in some other features from the legacy RX path:
* wrap the RX proc calls in the RX refcount;
* call the DFS checking, fast frames staging and TX rescheduling if
  required.

TODO:

* figure out if I can just make "do TX rescheduling" mean "schedule
  TX taskqueue" ?
2012-07-14 07:56:47 +00:00
adrian
6036c7128d Make sure that 'rs' is pointing to the correct RX status. 2012-07-14 05:53:03 +00:00
adrian
852b8a4cb1 Ensure that error is set.
Noticed by:	rui
2012-07-14 05:51:54 +00:00
adrian
491bca3ef4 Change the RX EDMA path to first complete the FIFO, then re-populate it
with fresh descriptors, before handling the frames.

Wrap it all in the RX locks.

Since the FIFO is very shallow (16 for HP, 128 for LP) it needs to be
drained and replenished very quickly.  Ideally, I'll eventually move this
RX FIFO drain/fill into the interrupt handler, only deferring the actual
frame completion.
2012-07-14 02:52:48 +00:00
adrian
79bcabb67e Don't free the descriptor allocation/map if it doesn't exist.
I missed this in my previous commit.
2012-07-14 02:47:16 +00:00
adrian
1a7f56bc4c Create an RX queue lock.
Ideally these locks would go away and there'd be a single driver lock,
like what iwn(4) does.  I'll worry about that later.
2012-07-14 02:22:17 +00:00
adrian
00e578733c Fix EDMA RX to actually work without panicing the machine.
I was setting up the RX EDMA buffer to be 4096 bytes rather than the
RX data buffer portion.  The hardware was likely getting very confused
and DMAing descriptor portions into places it shouldn't, leading to
memory corruption and occasional panics.

Whilst here, don't bother allocating descriptors for the RX EDMA case.
We don't use those descriptors. Instead, just allocate ath_buf entries.
2012-07-14 02:07:51 +00:00
jhb
ec38b41c3e Cast a bus address to a uintmax_t for a debug printf to fix the build on
arm.
2012-07-11 15:04:20 +00:00
jhb
f7caeaead4 Map ATH_KTR_* to 0 when ATH_DEBUG is not defined. This effectively NOPs
out their use in that case.
2012-07-11 12:10:13 +00:00
jhb
26b7689ce1 Fix build when ATH_DEBUG is not defined. 2012-07-10 18:57:05 +00:00
adrian
673c1e65d7 Commit missing flags for the high/low priority (HP/LP) RX queues.
Noticed by:	everyone
2012-07-10 18:30:20 +00:00
adrian
1e8e6a0b77 Add some debugging and comments about what's going on when reinitialising
the FIFO.

I still see some corner cases where no RX occurs when it should be
occuring.  It's quite possible that there's a subtle race condition
somewhere; or maybe I'm not programming the RX queues right.

There's also no locking here yet, so any reset/configuration path
state change (ie, enabling/disabling receive from the ioctl, net80211
taskqueue, etc) could quite possibly confuse things.
2012-07-10 07:45:47 +00:00
adrian
f0a77e77df Flip on EDMA RX of both HP and LP queue frames.
Yes, this is in the legacy interrupt path.  The NIC does support
MSI but I haven't yet sat down and written that code.
2012-07-10 07:43:31 +00:00
adrian
b89b88c83b Migrate the ATH_KTR_* fields out to if_ath_debug.h . 2012-07-10 06:11:39 +00:00
adrian
74cba80cf0 Print the TX buffer if this error condition is asserted.
I need to figure out why this is occuring.  Hopefully I can get enough
descriptor dumps to figure it out.
2012-07-10 06:10:49 +00:00
adrian
4ac74af2a9 Add/fix EDMA RX behaviour.
* For now, kickpcu should hopefully just do nothing - the PCU doesn't need
  'kicking' for Osprey and later NICs. The PCU will just restart once
  the next FIFO entry is pushed in.

* Teach "proc" about "dosched", so it can be used to just flush the
  FIFO contents without adding new FIFO entries.

* .. and now, implement the RX "flush" routine.

* Re-initialise the FIFO contents if the FIFO is empty (the DP is NULL.)
  When PCU RX is disabled (ie, writing RX_D to the RX configuration
  register) then the FIFO will be completely emptied.  If the software FIFO
  is full, then no further descriptors are pushed into the FIFO and
  things stall.

This all requires much, much more thorough stress testing.
2012-07-10 06:05:42 +00:00
adrian
af0280285f Reorder these so they match the capability enum order. 2012-07-10 03:48:07 +00:00
adrian
782d38e70a Implement EDMA RX for AR93xx and later chips.
This is inspired by ath9k and the reference driver, but it's a new
implementation of the RX FIFO handling.

This has some issues - notably the FIFO needs to be reprogrammed when
the chip is reset.
2012-07-10 00:08:39 +00:00
adrian
5dbf12e2ad Convert sc_rxpending to a per-EDMA queue, and use that for the legacy code.
Prepare ath_rx_pkt() to handle multiple RX queues, and default the legacy
RX queue to use the HP queue.
2012-07-10 00:02:19 +00:00
adrian
6b825e43a0 Add some AR9300 HAL descriptor definition changes.
* Add a couple of RX errors;
* Add the spectral scan PHY error code;
* extend the RX flags to be a 16 bit field, rather than an 8 bit field;
* Add a new RX flag.

Obtained from:	Qualcomm Atheros
2012-07-09 23:58:22 +00:00
adrian
2977d109d8 Further preparations for the RX EDMA support.
Break out the DMA descriptor setup/teardown code into a method.
The EDMA RX code doesn't allocate descriptors, just ath_buf entries.
2012-07-09 08:37:59 +00:00
adrian
90ac8e0adb Introduce the EDMA related HAL capabilities.
Whilst here, fix a typo in a previous commit.

Obtained from:	Qualcomm Atheros
2012-07-09 07:31:26 +00:00
adrian
de86634e9a Extend the RX HAL API to include the RX queue identifier.
The AR93xx and later chips support two RX FIFO queues - a high and low
priority queue.

For legacy chips, just assume the queues are high priority.

This is inspired by the reference driver but is a reimplementation of
the API and code.
2012-07-09 07:19:11 +00:00
adrian
fd33b54fca Extend the debugging flags to include some AR9300 HAL related options.
Obtained from:	Qualcomm Atheros
2012-07-09 06:41:18 +00:00
adrian
682d2c5a3b Extend the RX descriptor completion debugging to log the larger
AR93xx receive descriptors.

This isn't entirely complete - the AR93xx and later descriptors
don't have a link/buffer pointer; the descriptor contents just
start.
2012-07-09 06:39:46 +00:00
adrian
a596d3e5b3 Add a debug category for RX EDMA. 2012-07-09 05:23:02 +00:00
adrian
8af1316f3a Begin abstracting out the RX path in preparation for RX EDMA support.
The RX EDMA support requires a modified approach to the RX descriptor
handling.

Specifically:

* There's now two RX queues - high and low priority;
* The RX queues are implemented as FIFOs; they're now an array of pointers
  to buffers;
* .. and the RX buffer and descriptor are in the same "buffer", rather than
  being separate.

So to that end, this commit abstracts out most of the RX related functions
from the bulk of the driver.  Notably, the RX DMA/buffer allocation isn't
updated, primarily because I haven't yet fleshed out what it should look
like.

Whilst I'm here, create a set of matching but mostly unimplemented EDMA
stubs.

Tested:

  * AR9280, station mode

TODO:

  * Thorough AP and other mode testing for non-EDMA chips;
  * Figure out how to allocate RX buffers suitable for RX EDMA, including
    correctly setting the mbuf length to compensate for the RX descriptor
    and completion status area.
2012-07-03 06:59:12 +00:00
adrian
3543a6a83d .. And fix another typo. Grr. 2012-07-02 06:07:46 +00:00
adrian
dfec3def9a Fix another typo. 2012-07-02 06:06:27 +00:00
adrian
614d3d6a0e Fix typo. 2012-07-02 06:05:25 +00:00
adrian
7222dd809d Bring over some further HAL capabilities from the Atheros HAL, as well
as an EDMA check function.

For the AR9003 and later NICs, different TX/RX DMA and descriptor handling
code will be conditional on the EDMA check.

Obtained from:	Qualcomm Atheros
2012-07-02 06:02:12 +00:00
adrian
6a3edead78 Add in some further changes from the AR9300 HAL:
* Add a new ANI variable, for AR9003 and later chips;
* The AR9003 and later series chips support two RX queues now, so start
  down the road of supporting that;
* Add some new TX queue types - uAPSD is possible on earlier chips,
  but PAPRD is relevant to AR9003 and later.

Obtained from:	Qualcomm Atheros, Linux ath9k
2012-07-01 05:14:24 +00:00
adrian
4eb10c74bc Migrate the MAC/BB hang structures out from ar5416_misc.h into the HAL.
The ar9300 HAL also uses these types, so it makes no sense to duplicate
them.
2012-07-01 03:15:18 +00:00
adrian
5d4bc9f384 Bring over capabilities for the AR9300 and later HAL. 2012-07-01 02:44:36 +00:00