4 Commits

Author SHA1 Message Date
tmm
e5e9ae1dc2 Add two new workaround for firmware anomalies:
1. At least some Netra t1 models have PCI buses with no associated
   interrupt map, but obviously expect the PCI swizzle to be done with
   the interrupt number from the higher level as intpin. In this case,
   the mapping also needs to continue at parent bus nodes.
   To handle that, add a quirk table based on the "name" property of
   the root node to avoid breaking other boxen. This property is now
   retrieved and printed at boot.
2. On SPARCengine Ultra AX machines, interrupt numbers are not mapped
   at all, and full interrupt numbers (not just INOs) are given in
   the interrupt properties. This is more or less cosmetical; the
   PCI interrupt numbers would be wrong, but the psycho resource
   allocation method would pass the right numbers on anyway.

Tested by:	mux (1), Maxim Mazurok <maxim@km.ua> (2)
2002-11-07 16:07:46 +00:00
jake
5d43846206 Identify UltraSPARC-III and UltraSPARC-III+ cpus. 2002-07-13 03:23:29 +00:00
tmm
1f20dab185 Define constants for the CPU implementation id; export the dectected id
as cpu_impl.
2002-02-13 15:47:12 +00:00
jake
fa2bcfc98d Move %ver definitions from pstate.h to ver.h. Add definitions for normal
kernel pstate values, which include a memory store order override.
2001-09-03 22:36:11 +00:00