Commit Graph

327 Commits

Author SHA1 Message Date
yongari
26fe9e04f8 Add F1 PHY found on Atheros AR8151 v2.0 PCIe gigabit ethernet
controller.
2010-08-09 17:22:14 +00:00
yongari
9533954d59 Marvell model number 0x06 is 88E1101 PHY. 2010-08-07 23:16:21 +00:00
yongari
042dce9b96 Add Marvell PHYG65G Gigabit PHY which is found on 88E8059 Yukon Optima.
Tested by:	James LaLagna < jameslalagna <> gmail dot com >
MFC after:	5 days
2010-04-30 19:01:55 +00:00
davidch
104994efcf - Pass flow control settings back to bce(4).
MFC after:	Two weeks
2010-04-29 22:00:57 +00:00
yongari
84c2817c79 Add Agere ET1011 PHY which is found on Belkin F5D5055 USB
controller. Unlike Agere ET1011C, Agere ET1011 does not seem to
need special DSP programming to workaround silicon bug.
2010-04-13 20:07:52 +00:00
davidch
e39966f0ea - Added support for 5709S/5716S PHYs.
Submitted by:	pyunyh
MFC after:	2 weeks
2010-03-18 20:57:57 +00:00
ed
fbf3d99d10 Remove an unneeded variable.
Reported by:	tinderbox
2010-03-18 07:35:20 +00:00
imp
b55593dee5 Remove two instances of the evil hack to get the ifnet. mii_ifp is
set early enough that we don't need to do these hacks anymore.
2010-03-17 22:45:53 +00:00
qingli
8134df93ab Set the device capabilities to include dynamic link-state for
those modern drivers.

Reviewed by:	imp (and suggested by imp)
MFC after:	3 days
2010-03-17 22:12:12 +00:00
sobomax
39f5294e3c Fix style(9) bugs in the previous revision. 2010-03-10 23:02:06 +00:00
sobomax
e530af564e further narrow down no carrier workaround, since it appears to only affect
very specific IBM hardware and other machines with the same BCM ASIC chip id
0x57081021 are just fine.

MFC after:	1 month
2010-03-10 23:00:15 +00:00
sobomax
58e98b40d2 Provide workaround for the ages old bug affecting certain BCM5708S
chip revision often found in the blades and resulting in interfaces
not sensing carrier signal. Looking at all problem reports it
appears that it only affects some very specific silicon revision
(ASIC (0x57081021); Rev (B2)) and version of the PHY that
supports 1000baseSX-FDX media only. Therefore, narrow the scope of
workaround to combination of that revision and media type. Given
that the first report on this issue is dated back to 2007, there is
not much hope that this issue will ever be properly resolved.

Among affected systems are IBM HS21, Intel SBXD132 and HP BL460c.

PR:		118238, 122551, 140970
MFC after:	1 month
2010-03-10 05:19:14 +00:00
yongari
06472b9695 Remove programming LED register and enable 25MHz TX clock for
88E1149 PHY. This will fix intermittent watchdog timeouts as well
as very slow network performance on 88E8072 Yukon Extreme.

PR:	kern/144148
MFC after:	1 week
2010-03-03 17:56:52 +00:00
joel
2e980c4bcf The NetBSD Foundation has granted permission to remove clause 3 and 4 from
the software.

Obtained from:	NetBSD
2010-03-03 17:55:51 +00:00
marius
de671b7499 Add support for BCM54K2 found in combination with Apple K2 GMAC.
Submitted by:   Andreas Tobler
Obtained from:  OpenBSD
MFC after:      1 week
2010-02-20 22:01:24 +00:00
yongari
5c6f3b356c Add check for fiber mode for BCM5714 PHY. This PHY supports both
copper and fiber interfaces over GMII so an explicit check is
necessary to know whether it was configured for fiber interface.
This change make BCM5715S work.

Tested by:	olli
MFC after:	1 week
2010-01-14 19:14:24 +00:00
yongari
4d5d27ed38 Add BCM5754 PHY id that is found on Dell Studio XPS 16.
Tested by:	scf
MFC after:	1 week
2010-01-14 00:36:49 +00:00
imp
560e1299d3 cardbus -> CardBus 2010-01-03 23:31:58 +00:00
yongari
a86f0364ea Make sure to enable Next Page bit for IP1001. Otherwise the PHY
fails to re-establishe 1000baseT link after downgrading to
10/100Mbps link.
2009-12-18 21:57:51 +00:00
yongari
634b156082 Add BCM5761 PHY id. 2009-11-02 18:15:11 +00:00
yongari
7139323b97 Add hack to pass controller specific information to phy driver.
Unlike most other PHYs there is no easy way to know which media
type the PHY supports on Marvell PHYs. MIIF_HAVEFIBER flags is now
passed via bus-specific instance variable of a device. While I'm
here add 88E1112 specific work around to set SIGDET polarity low.
Many thanks "Eugene Perevyazko <john <> dnepro dot net>" who kindly
gave remote access to system with DGE-560SX.
2009-09-28 21:03:28 +00:00
yongari
9c528dca41 Some fiber PHY(88E1112) does not seem to set resolved speed so
always assume we've got IFM_1000_SX.
2009-09-28 19:53:53 +00:00
yongari
898fa4c915 Don't encode model id twice.
Reported by:	Kristof Provost <kristof <> sigsegv dot be>
2009-09-28 19:48:17 +00:00
yongari
55fac3f9e0 Backout r193289. r193289 restored page select bits to previous
value instead of blindly resetting it to 0. However, it seems page
select bits of some 88E1116 PHY is initialized to invalid one such
that restoring page select bits after programming broke MII
register access. The correct solution would be reset page select
bits to 0 in PHY attach stage but it would require more testing.
Since we're in BETA stage such a change would be dangerous so just
back it out.
This change should fix nfe(4) breakage on NVIDIA MCP55.

Reported by:	Ryan Rogers < webmaster <> doghouserepair dot com >
		Sam Fourman Jr. < sfourman <> gmail dot com >
Tested by:	Ryan Rogers < webmaster <> doghouserepair dot com >
		Sam Fourman Jr. < sfourman <> gmail dot com >
Approved by:	re (kib)
2009-08-18 20:20:15 +00:00
marius
d0f0da4e4f - Also probe DP83865, which is an is an ultra low power version
of the DP83861 and DP83891.
- Reset the PHY during attach so it's in a known state.
- Add a comment describing why we hardwire 10baseT support in
  the BMSR.
- Always explicitly set IFM_HDX for half-duplex. [1]

Obtained from:	OpenBSD [1]
MFC after:	2 weeks
2009-06-13 23:27:04 +00:00
yongari
97e535876e Program LED registers for 88E1116/88E1149 PHYs. These PHYs are
found on Marvell Yukon Ultra, Marvell Yukon Extreme controllers.
While I'm here explicitly issue 'powerup' command for 88E1149 PHY.

Tested by:	jhb, Warren Block ( wblock <> wonkity dot com )
2009-06-02 00:30:30 +00:00
yongari
bd9aa35723 Don't assume page register value is 0 and restore previous page
register after issuing 'powerup'.
2009-06-02 00:21:30 +00:00
yongari
b9dc9ef823 Add driver support for 88E3016 PHY which is found on Marvell Yukon
FE+ controller. Due to the severe silicon bugs for Yukon FE+,
88E3016 seems to require more workarounds. However I'm not sure
whether the workaround is PHY specific or only applicable to Yukon
FE+. The datasheet for the PHY is publicly available but it lacks
several details for the workaround used in this change. The
workaround information was obtained from Linux. Many thanks to
Yukon FE+ users who helped me add 88E3016 support.

Tested by:	bz, Tanguy Bouzeloc ( the.zauron <> gmail dot com )
		Bruce Cran ( bruce <> cran dot org dot uk )
		Michael Reifenberger ( mike <> reifenberger dot com )
		Stephen Montgomery-Smith ( stephen <> missouri dot edu )
2009-05-25 02:36:29 +00:00
yongari
fd45d782d1 Do not ignore NEXT Page capability of auto-negotiation
advertisement register. Some PHYs such as 88E3016 requires NEXT
Page capability to establish valid link. Also set protocol selector
field which is read only but it makes the intention clearer.
2009-05-25 02:05:00 +00:00
yongari
544e2eb41a Don't read unnecessary PHY registers. Speed/duplex resolution bit
is valid only for auto-negotiation case so check the bit if we know
auto-negotiation is active. While I'm here explicitly checks
current speed with speed mask and set IFM_NONE if resolved speed
is unknown.
2009-05-25 01:56:19 +00:00
yongari
9d2ba51089 Report current link state while auto-negotiation is in progress. 2009-05-25 01:45:28 +00:00
yongari
fd66a376f6 Use mii_phy_add_media() and remove usage of local macro ADD. Also
checks extended status register to see whether the PHY is fast
ethernet or not. This removes a lot of checks for specific PHY
models and it makes easy to add more PHYs to e1000phy(4).

While I'm here remove setting mii_anegticks as it is set with
mii_phy_add_media().
2009-05-25 01:41:05 +00:00
imp
763ef5e40e New PHY driver for the internal PHY found in the AX88790. There's a
number of quirks for this device, and this implements just the basics.
The 2.5s powerdown recommended in the datasheet will be next...
2009-03-30 16:01:09 +00:00
imp
25dbf8cb6c Add PHY entry for the ASIX 88x90 internal PHYs. 2009-03-30 01:47:32 +00:00
yongari
4e908eaace For IP1001 PHYs, read auto-negotiation advertisement register to
get default next page configuration. While I'm here explicitly set
IP1000PHY_ANAR_CSMA bit. This bit is read-only and always set
by hardware so setting it has no effect but it would clear the
intention. With this change controllers that couldn't establish
1000baseT link should work.

PR:	kern/130846
2009-03-09 08:17:46 +00:00
yongari
d3c51f44fd Use mii_phy_add_media() and remove setting each media type.
While I'm here, don't set mii_anegticks as it's set by
mii_phy_add_media().
2009-03-09 08:09:06 +00:00
yongari
a994e6e0ad For unknown speed, explicitly set IFM_NONE. 2009-03-09 08:01:40 +00:00
yongari
bbcecb3767 Report current link state while auto-negotiation is in progress. 2009-03-09 07:56:40 +00:00
bz
57874580d3 Renamed the FRAMELEN macro to TRUEPHY_FRAMELEN as for powerpc
it seems to be possible to collide with FRAMELEN from machine/frame.h.

Found by:	zec
2008-11-28 23:44:13 +00:00
yongari
a2018f7497 Use auto-negotiation for manual media type selection. This fixes
establishment of 10/100Mbps link on Atheros AR8121(L1E).
2008-10-25 06:39:17 +00:00
yongari
13ea6f6b0f Correct PHY description and OUI of VSC8211. Previously VSC8211 was
not recognized by ciphy(4) due to the incorrect OUI.

Reported by:	nork
Tested by:	nork
2008-10-23 01:27:15 +00:00
yongari
06e624317c Some 88E1149 PHY's page select is initialized to point to other
bank instead of copper/fiber bank which in turn resulted in
wrong registers were accessed during PHY operation. It is
believed that page 0 should be used for copper PHY so reinitialize
E1000_EADR to select default copper PHY.
This fixes link establishment issue of nfe(4) on Sun Fire X4140.

OpenBSD also has similimar patch but they just reset the E1000_EADR
register to page 0. However some Marvell PHYs((88E3082, 88E1000)
don't have the extended address register and the meaning of the
register is quite different for each PHY model. So selecting copper
PHY is limited to 88E1149 PHY which seems to be the only one that
exhibits link establishment problem. If parent device know the type
of PHY(either copper or fiber) that information should be notified
to PHY driver but there is no good way to pass this information yet.

Reported by:	thompsa
Reviewed by:	thompsa
2008-10-17 05:26:51 +00:00
stas
2a2b3ea928 - Add driver for Attansic L2 FastEthernet controller found on
Asus EeePC and some Asus mainboards.

Reviewed by:	yongari, rpaulo, jhb
Tested by:	many
Approved by:	kib (mentor)
MFC after:	1 week
2008-10-03 10:31:31 +00:00
yongari
a635b04c3f Save extended address register prior to switching to 1000BASE-X
only mode and restore original value of extended address register
instead of overwriting it with page 1. There are still instance
information passing issue(e.g configured media type: fiber or
copper) from driver to PHY layer but this change make the selected
PHY work with 88E1112 PHY.

Reported by:	Krzysztof Jedruczyk < beaker <at> hot dot pl >
Tested by:	Krzysztof Jedruczyk < beaker <at> hot dot pl >
2008-09-30 08:18:38 +00:00
yongari
cee43dc76f Add Vitesse VSC8211 PHY which is found on Planex GU-1000T.
HW donated by:	nork
2008-09-30 07:30:05 +00:00
yongari
d19413df9c Explicitly mark IFM_HDX for half-duplex media. 2008-09-30 07:24:20 +00:00
yongari
6b5a450046 Report current link state while auto-negotiation is in progress. 2008-09-30 07:22:02 +00:00
yongari
fcbe6077bf Use mii_anegticks instead of hardcoded MII_ANEGTICKS. 2008-09-30 07:20:26 +00:00
yongari
125f95a1fb Announce link loss right after it happens. 2008-09-30 07:19:01 +00:00
raj
92fbe03257 Recognize 88E1116R phy variation. This part is found on some embedded devices.
Obtained from:	Semihalf
2008-09-04 11:09:40 +00:00