Commit Graph

8 Commits

Author SHA1 Message Date
Michal Meloun
b0352107f1 Add support for RK3288 SoC. 2020-12-04 16:24:44 +00:00
Emmanuel Vadot
e213223c9b Remove "all rights reserved" from copyright for the file I own.
Some of the files have both me and Jared McNeill and he gave me
permission to remove it from his files too.
2019-12-03 21:00:45 +00:00
Michal Meloun
fa2ec6b439 Finish implementation of RK3299 clocks.
- implement of all but mmc clocks. MMC clocks will be added later by own commit.
- use 'link' clock type for external clocks.
- use macros for initialization of structure's named members.

MFC after:	3 weeks
Reviewed by:	manu
Differential Revision:  https://reviews.freebsd.org/D22441
2019-11-26 17:56:39 +00:00
Michal Meloun
c32081614b Enhance Rockchip clocks implementation.
- add support for fractional dividers
- allow to declare fixed and linked clock

MFC after:	3 weeks
Reviewed by:	manu
Differential Revision:  https://reviews.freebsd.org/D22282
2019-11-08 19:13:11 +00:00
Emmanuel Vadot
78a2a6b613 arm64: rockchip: Implement resets
Module resets where not implemented when rockchip clocks were commited.
Implement them.
Since all resets registers are contiguous a driver only need to give
the start offset and the number of resets. This avoid to have to declare
every resets.
2019-09-28 22:19:52 +00:00
Emmanuel Vadot
c3aec23870 arm64: rockchip: Add RK3399_CLK_PLL
PLLs on the RK3399 are different than the ones on the RK3328.
Add a new type and some dedicated recalc and set_freq functions.
Rename the RK3328 dedicated rk_clk_pll function with rk3328_ prefix.

MFC after:	1 month
2018-12-01 20:26:59 +00:00
Emmanuel Vadot
3df266dff9 arm64: rockchip: Add proper armclock support
The core clock (armclk) on RockChip SoC is special.
It can derive it's clock from many PLLs but RockChip recommand to do it
from "apll" on old SoC and "npll" on new SoC. The reason for choosing npll
is that it's have less jitter and is more close to the arm core on the SoC.
r333314 added the core clock as a composite clock but due to it's specials
property we need to deal with it differently.
A new rk_clk_armclk type is added for this and it supports only the "npll"
as we don't run on old RockChip SoC that only have the "apll".
It will always reparent to "npll" and set the frequency according to a rate
table that is known to be good.
For now we set the "npll" to the desired frequency and just set the core clk
divider to 1 as its parent it just used for the core clk.
2018-05-23 19:07:03 +00:00
Emmanuel Vadot
2a3d5e3364 rk3328: Add support for this SoC
* rk_cru is a cru driver that needs to be subclassed by
  the real CRU driver
* rk_clk_pll handle the pll type clock on RockChip SoC, it's only read
  only for now.
* rk_clk_composite handle the different composite clock types (with gate,
  with mux etc ...)
* rk_clk_gate handle the RockChip gates
* rk_clk_mux handle the RockChip muxes (unused for now)
* Only clocks for supported devices are supported for now, the rest will be
  added when driver support comes
* The assigned-clock* property are not handled for now so we rely a lot on the
  bootloader to setup some initial values for some clocks.
2018-02-26 21:25:50 +00:00