o recognize ixp435 cpu
o change memory layout for for ixp4xx to not assume memory is aliases
to 0x10000000 (Cambria/ixp435 memory starts at zero)
o handle 64 irqs for ixp435
o dual EHCI USB 2.0 controller integral to ixp435
o overhaul NPE code for ixp435 and better MAC+MII naming
o updated NPE firmware (including NPE-A image for ixp435/ixp465)
o Gateworks Cambria board support:
- IDE compact flash
- MCU
- front panel LED on i2c bus
- Octal LED latch
Sanity-tested with NFS-root on Avila and Cambria boards. Requires
pending boot2 mods for CF-boot on Cambria.
module; the ath module now brings in the hal support. Kernel
config files are almost backwards compatible; supplying
device ath_hal
gives you the same chip support that the binary hal did but you
must also include
options AH_SUPPORT_AR5416
to enable the extended format descriptors used by 11n parts.
It is now possible to control the chip support included in a
build by specifying exactly which chips are to be supported
in the config file; consult ath_hal(4) for information.
contents.
- It is possible to override the dynamic configuration by using
AT91C_MAIN_CLOCK option in kernel config.
PR: arm/128961 (based on)
Submitted by: Bjorn Konig <bkoenig@alpha-tierchen.de>
Reviewed by: imp
Approved by: kib (mentor, implicit)
o Copy kb920x_machdep.c to at91_machdep.c
o Move board_init to new board_kb920x.c
o rename ramsize to at91_ramsize and make it accessible to board_* files.
o Delete files.kb920x. We can do this selection with the new boards.
o Add a stub for the tsc4370 board init, which will be added in
a future commit.
o Add new 'devices' at91_board_kb920x and at91_board_tsc4370. More are
needed and will be added in future commits.
Reviewed by: stass, cognet
of the ABI of the currently executing image. Change some places to test
the flags instead of explicit comparing with address of known sysentvec
structures to determine ABI features.
Discussed with: dchagin, imp, jhb, peter
and ifnet functions
- add memory barriers to <machine/atomic.h>
- update drivers to only conditionally define their own
- add lockless producer / consumer ring buffer
- remove ring buffer implementation from cxgb and update its callers
- add if_transmit(struct ifnet *ifp, struct mbuf *m) to ifnet to
allow drivers to efficiently manage multiple hardware queues
(i.e. not serialize all packets through one ifq)
- expose if_qflush to allow drivers to flush any driver managed queues
This work was supported by Bitgravity Inc. and Chelsio Inc.
sdhci supports up to 65535 blocks transfers, at91_mci - one block.
Enable multiblock operations disabled before to follow at91_mci driver
limitations.
Reviewed by: imp@
machine arm
device mem
options GEOM_BSD
options GEOM_MBR
Remove the first two from all kernel configuration files and
change geom_bsd and geom_mbr from standard to optional.
This uses the common U-Boot support lib (sys/boot/uboot, already used on
FreeBSD/powerpc), and assumes the underlying firmware has the modern API for
stand-alone apps enabled in the config (CONFIG_API).
Only netbooting is supported at the moment.
Obtained from: Marvell, Semihalf
FreeBSD 8-CURRENT was tested and run successfully on the following eval
boards and devices :
* DB-88F5182, DB-88F5281 (Orion based)
* DB-88F6281, RD-88F6281 (Kirkwood based)
* DB-78100 (Discovery based)
For more detailed info on build instructions and other examples please refer
to http://wiki.freebsd.org/FreeBSDMarvell
Obtained from: Marvell, Semihalf
* Orion
- 88F5181
- 88F5182
- 88F5281
* Kirkwood
- 88F6281
* Discovery
- MV78100
The above families of SOCs are built around CPU cores compliant with ARMv5TE
instruction set architecture definition. They share a number of integrated
peripherals. This commit brings support for the following basic elements:
* GPIO
* Interrupt controller
* L1, L2 cache
* Timers, watchdog, RTC
* TWSI (I2C)
* UART
Other peripherals drivers will be introduced separately.
Reviewed by: imp, marcel, stass (Thanks guys!)
Obtained from: Marvell, Semihalf
The physical page which we clear is accessed via additional temp kernel
mapping for the period of zeroing operation. However in systems with virtual
d-cache (most ARMs) when write-allocate feature is enabled, we can have
modified but unflushed content pertaining to this physical page still in the
d-cache due to its primary (pre-existing) mapping. In such scenario that
cached content upon flush is likely to overwrite [portions of] the physical
page we want to zero here..
This is a general problem with multiple virtual mappings covering the same
physical page with write-allocate and virtual d-cache: there is inherent
potential for corruptions of this kind, which are not easily resolved; it is
best policy that such multiple mappings be not allowed.
Obtained from: Marvell, Semihalf
