7 Commits

Author	SHA1	Message	Date
sbruno	577b42d393	Update hwpmc to support the Xeon class of Ivybridge processors. ... case 0x3E: /* Per Intel document 325462-045US 01/2013. */ Add manpage to document all the goodness that is available in this processor model. No support for uncore events at this time. Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: davide, jimharris, sbruno Obtained from: Yahoo! Inc. MFC after: 2 weeks	2013-01-31 22:09:53 +00:00
sbruno	88f73ca292	Cleanup and rename some variables in libpmc and hwpmc. ... Submitted by: hiren panchasara <hiren.panchasara@gmail.com> Reviewed by: jimharris@ sbruno@ Obtained from: Yahoo! Inc. MFC after: 2 weeks	2012-10-24 01:26:29 +00:00
sbruno	8d728b03ba	Update man page crossreferences to sandybridge xeon class ... MFC after: 2 weeks	2012-10-19 17:21:10 +00:00
fabient	2a46ae3db5	Add Intel Ivy Bridge support to hwpmc(9). ... Update offcore RSP token for Sandy Bridge. Note: No uncore support. Will works on Family 6 Model 3a. MFC after: 1 month Tested by: bapt, grehan	2012-09-06 13:54:01 +00:00
fabient	5edfb77dd3	Add software PMC support. ... New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month	2012-03-28 20:58:30 +00:00
pluknet	e2d16db0bd	Kill EoL whitespaces, and minor lint.	2012-03-02 05:55:45 +00:00
davide	8636a37ecc	- Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) ... - New manpages with event lists. - Add MSRs for the Intel Sandy Bridge microarchitecture Reviewed by: attilio, brueffer, fabient Approved by: gnn (mentor) MFC after: 3 weeks	2012-03-01 21:23:26 +00:00