o improves understandability by replacing numerous relative address
calculations with fixed addresses; everything should now match up
more easily with the vm layout shown at the top of the file
o move the expansion bus chip select regions to be contiguous with
the expansion bus configuration area; this is not exploited right
now but allows map consolidation in the future
o leave a gap between the expansion bus regions and the pci config
space in case we want to map more exp bus cs regions
Reviewed by: imp, thompsa
usb stack rather than with the rest of the processor support code.
Not sure that's a good idea, as we were moving away from it, but this
fixes the build in the mean time so we can have that discussion.
the same dma tag. However, it can happen multiple dma tags share the same
bounce zone too, so add a per-bounce zone map counter, and check it instead of
the dma tag map counter, to know if we have to alloc more pages.
Reported by: miwi
Reviewed by: scottl
offset. This is needed for the ehci hardware buffer rings that assume
this behavior.
This is an interim solution, and a more general one is being worked
on. This solution doesn't break anything that doesn't ask for it
directly. The mbuf and uio variants with this flag likely don't work
and haven't been tested.
Universe builds with these changes. I don't have a huge-memory
machine to test these changes with, but will be happy to work with
folks that do and hps if this changes turns out not to be sufficient.
Submitted by: alfred@ from Hans Peter Selasky's original
o add bus shim for cfi driver
o add static mapping for CS0 (we map all 16M as the cfi driver doesn't
support demand mapping)
Note this needs some tweaking to work for 2358 boards which is why the
CAMBRIA config is not touched.
rather than a fixed 512... This fixes the mount root problem on at91.
Prior to the SD card reorg, all data transfers were 512 bytes, so we
didn't notice.
the serial port class when we set the devclass since it is now
no-longer a compile time constant. Eliminate the pci include, as it
isn't relevant or necessary.
time constant. This allows us to potentially change it at runtime or
autodetect it early in the boot (the latter being much more likely to
have a good outcome).
o Only set 4-bit caps on those boards that have 4-bit caps (this means that
because we don't set wire4 yet, this forces us to always use 1-bit bus).
o Don't test wire4 when setting up the bus width, since bad things will
happen if we do.
# This likely won't fix the busted at91 sd card support, but these are
# needful changes for correctness.
- The contents of 'feroceon_cpufuncs' dispatch table was really dedicated for the
new Sheeva CPU (in 88F6xxx and MV-78xxx SOCs), and NOT Feroceon.
- Feroceon CPU (in 88F5xxx SOCs) appears as a regular ARM926EJ-S core and does
not require dedicated routines.
This will be accompanied by a file rename commit.
- Provide dedicated rmans for MEM and IO resources.
- Convert PCI IRQ routing info into a table (from callback approach), provide
config data for alternative DB- boards.
- Fix a wrong boundary check error in pcib_mbus_init_bar()
Obtained from: Semihalf
- Allow for setting per platform MPP/GPIO configuration in the kernel, so
that we can override all settings firmware might set.
- Set decode windows for the remaining on-chip peripherals: CESA, SATA and XOR.
- Improve handling of USB controllers so that all port are available on the
given SOC/platform (e.g. up to three on DB-78xxx), this includes rework of
USB decode windows set-up.
- Other minor fixes and cosmetics.
Obtained from: Semihalf
- Clean up TCLK handling so that it's dynamically recognized depending on
registers settings or chip version/revision. Update registers definitions.
- Teach SOC ident routine about A0 (initial silicon version for general
audience)
Obtained from: Marvell, Semihalf
options. Using the already included std.avila is not considered
to be entirely right (and the options slightly differ) but the best
match we currently have. Upcoming work should fit better.
Reorder another variable to match the layout of other configs.
Reviewed by: sam, warner (earlier version with options removed)
FPA floating-point format is identical to the VFP format,
but is always stored in big-endian.
Introduce _IEEE_WORD_ORDER to describe the byte-order of
the FP representation.
Obtained from: Juniper Networks, Inc
o check feature bits when probing NPE ethernet support
o move firmware loading logic from if_npe to core npe support
o allow multiple refs to core NPE driver
o while here fix hw.npe.debug tunable path
o add definitions for more bits, for masking out IXP465-specific bits,
and %b format string
o add ixp4xx_read_feature_bits to retrieve the mask of valid features
(aka fuse bits)
o add cpu_is_ixp42x() macro
o print feature bits at boot
