This introduce an xxxFS_BOOT for each of the rootable filesystems.
(Presently not required, but encouraged to allow a smooth move of option *FS
to opt_dontuse.h later.)
LFS is temporarily disabled, and will be re-enabled tomorrow.
of multiple PCI IDE controllers(Dyson), and some updates and cleanups from
John Hood, who originally made our IDE DMA stuff work :-).
I have run tests with 7 IDE drives connected to my system, all in DMA
mode, with no errors. Modulo any bugs, this stuff makes IDE look
really good (within it's limitations.)
Submitted by: John Hood <cgull@smoke.marlboro.vt.us>
device probe of a host to PCI bridge may modify that value, based on
its knowledge of device specific registers. This makes the Intel XXpress
work, as verified by: Terje Marthinussen <terjem@cc.uit.no>.
1) Stop at the first map register that contains a zero value.
2) When testing for the map size work up from low values, since
this works around a bug in some BusLogic SCSI card, which has
the 16 upper port base address bits hardwired to zero.
The config register dump printed in the bootverbose case has
been slightly rearranged.
reality. There will be a new call interface, but for now the file
pci_compat.c (which is to be deleted, after all drivers are converted)
provides an emulation of the old PCI bus driver functions. The only
change that might be visible to drivers is, that the type pcici_t
(which had been meant to be just a handle, whose exact definition
should not be relied on), has been converted into a pcicfgregs* .
The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t
and has been converted to just call the PCI drivers functions to access
configuration space register, instead of inventing its own ...
This code is by no means complete, but assumed to be fully operational,
and brings the official code base more in line with my development code.
A new generic device descriptor data type has to be agreed on. The PCI
code will then use that data type to provide new functionality:
1) userconfig support
2) "wired" PCI devices
3) conflicts checking against ISA/EISA
4) maps will depend on the command register enable bits
5) PCI to Anything bridges can be defined as devices,
and are probed like any "standard" PCI device.
The following features are currently missing, but will be added back,
soon:
1) unknown device probe message
2) suppression of "mirrored" devices caused by ancient, broken chip-sets
This code relies on generic shared interrupt support just commited to
kern_intr.c (plus the modifications of isa.c and isa_device.h).
There are various options documented in i386/conf/LINT, there is more to
come over the next few days.
The kernel should run pretty much "as before" without the options to
activate SMP mode.
There are a handful of known "loose ends" that need to be fixed, but
have been put off since the SMP kernel is in a moderately good condition
at the moment.
This commit is the result of the tinkering and testing over the last 14
months by many people. A special thanks to Steve Passe for implementing
the APIC code!
This parameter is intended to allow new kernels to work with old LKM binaries,
provided the revision ID is incremented whenever the PCI LKM interface is
changed. The revision ID does not at all protect against changes in data
structures accesses by the driver.
This will make a number of things easier in the future, as well as (finally!)
avoiding the Id-smashing problem which has plagued developers for so long.
Boy, I'm glad we're not using sup anymore. This update would have been
insane otherwise.
bridges with support for 64 bit memory addresses and 32 bit I/O addresses).
The code is not complete. It ignores the upper half of the long addresses.
This is not a problem on PC compatible systems, but has to be fixed for
real computers.
Garrett Wollman sent me this code a few weeks ago for review, and I made
some significant changes, which he in turn accepted ...
In order to make use of these changes, a device entry has to added to /dev.
Submitted by: wollman
way it attaches multiple PCI buses directly to the CPU, instead of having
them hanging off from PCI to PCI bridges. This code is a hack, and will
be obsoleted by the planned rework of the PCI code, which will change the
dealing with PCI to PCI bridges and other special devices significantly.
The patch also adds a kern_devconf entry for PCI bus 0 which is assumed
to be a child of cpu0. The new PCI code will make it possible to hand out
the kern_devconf structure to a pci device being attached, since this is
(regretably, IMHO) required by a few ISA devices.
Finally there are new PCI ids for some Intel chip set devices, which had
already been known to 2.1.5R, but did not make it into -current. This closes
"kern/1558: PCI probe seems to have lost a device in -current".
should be <= than subordinate, not the other way around.
They are both true if the bridge is not cascaded (i.e., twin-channel
scsi/e-net adapters won't be affected by this bug), which is probably why
it was unnoticed until today.
- always use pci_conf_read() and pci_conf_write(). (This is required to
simulate non-existant devices in my system for PCI bridge code tests.)
- reorder some functions (put the main functions at the end).
- correct off by one bug in the code dealing with unitialized PCI to PCI
bridge chips. (Bug found by ASAMI Satoshi.)
- print function number for multi-function devices.
vm_offset_t is currently unsigned long but should probably be plain
unsigned for i386's to match the choice of minimal types to represent
for fixed-width types in Lite2. Anyway, it shouldn't be assumed
to be unsigned long.
I only fixed the type mismatches that were detected when I changed
vm_offset_t to unsigned. Only pointer type mismatches were detected.
port addresses (even though the PC architecture doesn't support them).
Add code to limit the I/O map size based on the lowest set bit of the
address. This cures the problem with the BT946C only having a 16 bit
map register, in voiolation of the PCI specs, without giving up the
general support of >65K port regions.
feature in the header type register, though it is required by the PCI spec.
This should correctly probe both functions of the Intel 82371FB chip,
without the need for a special case based on the device ID.
includes a hack in the probe code: the 82371FB is a multifuction
device, but doesn't properly set the configuration bit which
indicates this. So, we just hard-wire all 82371FBs as multifunction
devices.
This does not actually make the bus-master IDE stuff work, although
if anyone wants to work on that, I have the databooks that tell
how to use it.
