Commit Graph

16 Commits

Author SHA1 Message Date
cognet
02162f9242 Add two new options, FLASHADDR, which defines the address the flash is
mapped at, and LOADERRAMADDR, the address at which the loader maps the ram at
at the time the kernel is booted.
They are used to detect if the kernel is booted from the onboard flash.
Define those for the IQ31244
2007-02-19 01:03:08 +00:00
ticso
b2a331b15e MFp4: add BWCT kernel configuration 2007-01-05 02:08:35 +00:00
sam
ac8ac0205c add CPU_XSCALE_IXP425
Reviewed by:	cognet, imp
MFC after:	1 month
2006-11-19 23:56:44 +00:00
cognet
d4600e67df Finally bring it support for the i80219 XScale processor.
Submitted by:	Max M. Boyarov <m.boyarov bsd by>
2006-08-24 23:51:28 +00:00
cognet
2d628bb4d9 Rewrite ARM_USE_SMALL_ALLOC so that instead of the current behavior, it maps
whole the physical memory, cached, using 1MB section mappings. This reduces
the address space available for user processes a bit, but given the amount of
memory a typical arm machine has, it is not (yet) a big issue.
It then provides a uma_small_alloc() that works as it does for architectures
which have a direct mapping.
2006-08-08 20:59:38 +00:00
imp
6f36c78e6b For the moment, make board configuration a compile time option. This
saves space in the final kernel, but at the expense of flexibility to
boot the same kernel accross a family of boards.
2006-07-14 21:59:54 +00:00
cognet
13929c476a Convert the last offender, the SA1110 port, to ARM32_NEW_VM_LAYOUT, and
completely nuke the !ARM32_NEW_VM_LAYOUT case.
2006-06-06 21:06:57 +00:00
cognet
04175402f4 Make VERBOSE_INIT_ARM compile by fixing various printf formats, and add it
as an option.

Submitted by:   Max N. Boyarov <m.boyarov at bsd dot by>
2006-06-06 01:14:12 +00:00
cognet
2e58b61962 Resurrect Skyeye support :
Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds
workarounds for things skyeye doesn't simulate. Specifically :
- Use USART0 instead of DBGU as the console, make it not use DMA, and           manually provoke an interrupt when we're done in the transmit function.
- Skyeye maintains an internal counter for clock, but apparently there's
no way to access it, so hack the timecounter code to return a value which
is increased at every clock interrupts. This is gross, but I didn't find a
better way to implement timecounters without hacking Skyeye to get the
counter value.
- Force the write-back of PTEs once we're done writing them, even if they
are supposed to be write-through. I don't know why I have to do that.
2006-05-13 23:41:16 +00:00
cognet
067f218bcf Add a new option, XSCALE_DISABLE_CCNT, to not use the xscale ccnt as a
timecounter (because gxemul doesn't emule it yet).
2006-04-06 17:11:08 +00:00
cognet
24415ea106 The IQ80321 clock is 200MHz, but the IQ80321 is 198MHz, so add a kernel option
to override the frequency
2005-12-09 23:52:51 +00:00
cognet
6088d73c5f Add ARM_USE_SMALL_ALLOC. 2005-06-07 23:05:04 +00:00
cognet
67e8b297b9 Add a new option, ARM_CACHE_LOCK_ENABLE (I forgot it in my last commit). 2005-02-26 22:41:07 +00:00
cognet
735956cb8e Add a new option, ARM32_NEW_VM_LAYOUT. When set, we try to put up to 4
L2 tables in one page, instead of the old 1 L2 table <=> 1 page behavior.
While I'm there, add ARM9_CACHE_WRITE_THROUGH, which I forgot last time.
2004-11-10 22:08:27 +00:00
cognet
c04b68fd28 Add new options :
PHYSADDR : Address of the physical memory
KERNPHYSADDR : Physical address where the kernel starts
KERNVIRTADDR : Virtual address of the kernel
STARTUP_PAGETABLE_ADDR : Where to put the page table at bootstrap
+ Xscale specific options
2004-09-23 22:52:25 +00:00
cognet
e4128057bf Add config magic for arm. 2004-05-14 11:49:40 +00:00