to 0x600 via a 'rep movsw'. Once that was done, %cx was zero, so we could
simply use 'movb' to update the lower byte of %cx in preparation for
zeroing out the fake partition entry used to boot to other drives via F5.
Well, in the new boot0, we don't actually relocate ourselves, instead it
is easier to create the fake partition entry first and then just use it to
get the BIOS to load all of boot0 into memory at 0x600. However, since we
aren't doing the relocate code anymore, we don't know that %cx == 0 when
we hit the 'movb' to setup %cx for clearning the fake partition entry.
Thus, if %ch != 0 when the BIOS started boot0, then it would end up zeroing
a lot more memory than just 8 words. The solution is to do a word move of
$8 into %cx.
Debugging help from: David Wolfskill <dhw@whistle.com>
Linux kernel image, and is designed to be dropped into a Linux system
and booted via LILO. Once booted, the user is greeted by the FreeBSD
loader. This still isn't quite complete, as the the root= specification
from LILO isn't currently passed to the loader yet.
- Autodetection and support of the BIOS EDD extensions to work around the
1024 cylinder limit on all but really ancient BIOS's.
- To work around some BIOS's which break when EDD is used with older drives,
we only attempt to use EDD if the cylinder is > 1023.
- Since this new code required more space than we had left, expand boot0 to
2 sectors (1024 bytes) in length.
- Add support for boot0 being multiple sectors using predefined constants.
If boot0 needs to be extended in the future, all that is required is
bumping the NUM_SECTORS constant.
- Now that we have more room to work with, add a few more fs type
descriptions while making others more verbose.
use the BIOS Equipment List to determine how many hard drives are
installed and if the drive number we received in %dl is valid.
- Don't bother to disable interrupts when setting up the stack. The 8086
and beyond implicitly disable interrupts after an instruction that sets
%ss (for example, a pop or a mov) so that you can safely set %ss and %sp
in two consecutive instructions. An exception to this is the lss
instruction, which can set both registers simultaneously and thus doesn't
need this hack.
- Add support for EDD BIOS extensions to support booting off of hard drives
of nearly arbitrary length.
- Add in support for the EDD (Enhanced Disk Drive) BIOS extensions to
use LBA mode for accessing drives past cylinder 1024. This should allow
us to load a kernel from anywhere on a newer drive up to 2 TB. Part
of this came from the PR below.
PR: i386/13847
Submitted by: Tor Egge <Tor.Egge@fast.no>
theory, this should allow the K7V Athlon motherboard to boot ok with boot
virus protection enabled. However, I have no hardware to test this. It
shouldn't break anything though. :)
Prodded by: Kelly Yancey <kbyanc@posi.net>
with the new binutils. Now that we have a decent assembler, all the old
m4 macros are no longer needed. Instead, straight assembly can be used
since as(1) now understands 16-bit addressing, branches, etc. Also,
several bugs have been fixed in as(1), allowing boot0.s to be further
cleaned up.
code instead of using 32-bit code and having to just "know" that it's
really 16-bit instructions when things run. This also allows the code
to use fewer macros and more actual assembly statements, which eases
maintenance. Unfortunately, due to as(1) brokenness, we still use m4
macros for all 16-bit addresses, and all short jumps (i.e., 8-bit
relative addresses in the jump instruction) must be wrapped in .code32
directives to avoid useless bloat by as(1). This also fixes a few
problems that were preventing boot0 from compiling with the latest
and greatest version of as(1).
below). This did not work previously because interrupts were
disabled when PXE calls were being made, and they must be enabled.
This should also allow us to be compliant with all newer PXE rom's
from Intel.
For PXE 0.99, this has been tested using the Intel N440BX motherboard
and I am confident it will work on the Intel L440GX motherboard.
Lots of help/information from: jhb, peter
I would like to thank Michael Johnston <michael.johnston@intel.com>,
Mike Henry <mike.henry@intel.com>, and all the other PXE developers
at Intel for their help, and information in helping solve this
problem.
from user mode. Don't disable interrupts when returning from vm86 mode
to user mode either. Now, we only disable interrupts before calling a
hardware interrupt handler, which is the only time we _should_ be
disabling interrupts.
Because of this, err, feature, any routine that one called in vm86 mode
had to re-enable interrupts by setting the interrupt flag or interrupts
would remain disabled even after the routine returned. For example, I
have a simple debugging routine that uses a vm86 mode function to dump
any arbitrary memory word that I use to read the BIOS timer or any other
memory location. This function does 1 load instruction from memory and
then returns. Since it didn't re-enable interrupts, the first time I
called it to read the BIOS timer, it disabled interrupts. This also
affected the PXE bootstrap as it needs interrupts enabled while it is
processing. This patch fixes both of those situations so that those
functions do not worry about having to enable interrupts. Hardware
interrupt handlers worked fine with the old code because they always
enable interrupts as part of their routine.
If you have any problems with the loader after this commit, please
let me know. I'd like to MFC it in a week or two since PXE support
needs it.
Noticed by: ps, Michael Johnston <michael.johnston@intel.com>
