8c1e98efd7
The L3 cache controller (Corenet Platform Cache) is listed with one of its compatible strings as "cache", which this driver can't attach to. Restrict to a known list of primary cache controller strings, as found in the l2cache devicetree binding.
165 lines
5.1 KiB
C
165 lines
5.1 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018 Justin Hibbits
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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/*
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* From the P1022 manual, sequence for writing to L2CTL is:
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* - mbar
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* - isync
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* - write
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* - read
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* - mbar
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*/
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#define L2_CTL 0x0
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#define L2CTL_L2E 0x80000000
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#define L2CTL_L2I 0x40000000
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struct mpc85xx_cache_softc {
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struct resource *sc_mem;
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};
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static struct ofw_compat_data compats[] = {
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{"fsl,8540-l2-cache-controller", 1},
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{"fsl,8541-l2-cache-controller", 1},
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{"fsl,8544-l2-cache-controller", 1},
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{"fsl,8548-l2-cache-controller", 1},
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{"fsl,8555-l2-cache-controller", 1},
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{"fsl,8568-l2-cache-controller", 1},
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{"fsl,b4420-l2-cache-controller", 1},
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{"fsl,b4860-l2-cache-controller", 1},
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{"fsl,bsc9131-l2-cache-controller", 1},
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{"fsl,bsc9132-l2-cache-controller", 1},
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{"fsl,c293-l2-cache-controller", 1},
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{"fsl,mpc8536-l2-cache-controller", 1},
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{"fsl,mpc8540-l2-cache-controller", 1},
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{"fsl,mpc8541-l2-cache-controller", 1},
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{"fsl,mpc8544-l2-cache-controller", 1},
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{"fsl,mpc8548-l2-cache-controller", 1},
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{"fsl,mpc8555-l2-cache-controller", 1},
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{"fsl,mpc8560-l2-cache-controller", 1},
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{"fsl,mpc8568-l2-cache-controller", 1},
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{"fsl,mpc8569-l2-cache-controller", 1},
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{"fsl,mpc8572-l2-cache-controller", 1},
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{"fsl,p1010-l2-cache-controller", 1},
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{"fsl,p1011-l2-cache-controller", 1},
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{"fsl,p1012-l2-cache-controller", 1},
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{"fsl,p1013-l2-cache-controller", 1},
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{"fsl,p1014-l2-cache-controller", 1},
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{"fsl,p1015-l2-cache-controller", 1},
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{"fsl,p1016-l2-cache-controller", 1},
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{"fsl,p1020-l2-cache-controller", 1},
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{"fsl,p1021-l2-cache-controller", 1},
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{"fsl,p1022-l2-cache-controller", 1},
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{"fsl,p1023-l2-cache-controller", 1},
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{"fsl,p1024-l2-cache-controller", 1},
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{"fsl,p1025-l2-cache-controller", 1},
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{"fsl,p2010-l2-cache-controller", 1},
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{"fsl,p2020-l2-cache-controller", 1},
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{"fsl,t2080-l2-cache-controller", 1},
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{"fsl,t4240-l2-cache-controller", 1},
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{0, 0}
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};
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static int
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mpc85xx_cache_probe(device_t dev)
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{
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if (ofw_bus_search_compatible(dev, compats)->ocd_str == NULL)
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return (ENXIO);
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device_set_desc(dev, "MPC85xx L2 cache");
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return (0);
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}
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static int
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mpc85xx_cache_attach(device_t dev)
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{
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struct mpc85xx_cache_softc *sc = device_get_softc(dev);
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int rid;
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int cache_line_size, cache_size;
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/* Map registers. */
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rid = 0;
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sc->sc_mem = bus_alloc_resource_any(dev,
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SYS_RES_MEMORY, &rid, RF_ACTIVE);
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if (sc->sc_mem == NULL)
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return (ENOMEM);
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/* Enable cache and flash invalidate. */
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__asm __volatile ("mbar; isync" ::: "memory");
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bus_write_4(sc->sc_mem, L2_CTL, L2CTL_L2E | L2CTL_L2I);
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bus_read_4(sc->sc_mem, L2_CTL);
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__asm __volatile ("mbar" ::: "memory");
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cache_line_size = 0;
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cache_size = 0;
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OF_getencprop(ofw_bus_get_node(dev), "cache-size", &cache_size,
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sizeof(cache_size));
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OF_getencprop(ofw_bus_get_node(dev), "cache-line-size",
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&cache_line_size, sizeof(cache_line_size));
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if (cache_line_size != 0 && cache_size != 0)
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device_printf(dev,
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"L2 cache size: %dKB, cache line size: %d bytes\n",
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cache_size / 1024, cache_line_size);
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return (0);
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}
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static device_method_t mpc85xx_cache_methods[] = {
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/* device methods */
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DEVMETHOD(device_probe, mpc85xx_cache_probe),
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DEVMETHOD(device_attach, mpc85xx_cache_attach),
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DEVMETHOD_END
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};
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static driver_t mpc85xx_cache_driver = {
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"cache",
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mpc85xx_cache_methods,
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sizeof(struct mpc85xx_cache_softc),
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};
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static devclass_t mpc85xx_cache_devclass;
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EARLY_DRIVER_MODULE(mpc85xx_cache, simplebus, mpc85xx_cache_driver,
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mpc85xx_cache_devclass, NULL, NULL,
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BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
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