31fdf3d6d2
some unmerged interrupt status debugging code from my branch. * Add ah_intrstate[8] which will have the record of the last call to ath_hal_getintr(). * Wrap the KTR code behind ATH_KTR_INTR_DEBUG. * Add the HAL interrupt debugging behind AH_INTERRUPT_DEBUGGING. This is only done for the AR5416 and later NICs but it will be trivial to add to the earlier NICs if required. Neither are enabled by default, although to minimise HAL binary API differences, the ah_intrstate[] array is always compiled into the ath_hal struct.
367 lines
10 KiB
C
367 lines
10 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ar5416/ar5416.h"
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#include "ar5416/ar5416reg.h"
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/*
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* Checks to see if an interrupt is pending on our NIC
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*
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* Returns: TRUE if an interrupt is pending
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* FALSE if not
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*/
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HAL_BOOL
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ar5416IsInterruptPending(struct ath_hal *ah)
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{
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uint32_t isr;
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if (AR_SREV_HOWL(ah))
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return AH_TRUE;
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/*
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* Some platforms trigger our ISR before applying power to
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* the card, so make sure the INTPEND is really 1, not 0xffffffff.
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*/
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isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
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if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_MAC_IRQ) != 0)
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return AH_TRUE;
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isr = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
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if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_SYNC_DEFAULT))
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return AH_TRUE;
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return AH_FALSE;
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}
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/*
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* Reads the Interrupt Status Register value from the NIC, thus deasserting
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* the interrupt line, and returns both the masked and unmasked mapped ISR
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* values. The value returned is mapped to abstract the hw-specific bit
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* locations in the Interrupt Status Register.
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*
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* (*masked) is cleared on initial call.
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*
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* Returns: A hardware-abstracted bitmap of all non-masked-out
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* interrupts pending, as well as an unmasked value
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*/
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HAL_BOOL
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ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
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{
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uint32_t isr, isr0, isr1, sync_cause = 0;
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HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
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#ifdef AH_INTERRUPT_DEBUGGING
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/*
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* Blank the interrupt debugging area regardless.
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*/
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bzero(&ah->ah_intrstate, sizeof(ah->ah_intrstate));
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#endif
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/*
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* Verify there's a mac interrupt and the RTC is on.
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*/
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if (AR_SREV_HOWL(ah)) {
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*masked = 0;
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isr = OS_REG_READ(ah, AR_ISR);
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} else {
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if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) &&
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(OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON)
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isr = OS_REG_READ(ah, AR_ISR);
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else
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isr = 0;
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sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
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sync_cause &= AR_INTR_SYNC_DEFAULT;
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*masked = 0;
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if (isr == 0 && sync_cause == 0)
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return AH_FALSE;
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}
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#ifdef AH_INTERRUPT_DEBUGGING
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ah->ah_intrstate[0] = isr;
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ah->ah_intrstate[1] = OS_REG_READ(ah, AR_ISR_S0);
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ah->ah_intrstate[2] = OS_REG_READ(ah, AR_ISR_S1);
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ah->ah_intrstate[3] = OS_REG_READ(ah, AR_ISR_S2);
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ah->ah_intrstate[4] = OS_REG_READ(ah, AR_ISR_S3);
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ah->ah_intrstate[5] = OS_REG_READ(ah, AR_ISR_S4);
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ah->ah_intrstate[6] = OS_REG_READ(ah, AR_ISR_S5);
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#endif
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if (isr != 0) {
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struct ath_hal_5212 *ahp = AH5212(ah);
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uint32_t mask2;
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mask2 = 0;
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if (isr & AR_ISR_BCNMISC) {
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uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2);
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if (isr2 & AR_ISR_S2_TIM)
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mask2 |= HAL_INT_TIM;
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if (isr2 & AR_ISR_S2_DTIM)
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mask2 |= HAL_INT_DTIM;
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if (isr2 & AR_ISR_S2_DTIMSYNC)
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mask2 |= HAL_INT_DTIMSYNC;
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if (isr2 & (AR_ISR_S2_CABEND ))
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mask2 |= HAL_INT_CABEND;
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if (isr2 & AR_ISR_S2_GTT)
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mask2 |= HAL_INT_GTT;
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if (isr2 & AR_ISR_S2_CST)
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mask2 |= HAL_INT_CST;
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if (isr2 & AR_ISR_S2_TSFOOR)
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mask2 |= HAL_INT_TSFOOR;
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/*
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* Don't mask out AR_BCNMISC; instead mask
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* out what causes it.
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*/
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OS_REG_WRITE(ah, AR_ISR_S2, isr2);
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isr &= ~AR_ISR_BCNMISC;
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}
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if (isr == 0xffffffff) {
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*masked = 0;
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return AH_FALSE;
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}
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*masked = isr & HAL_INT_COMMON;
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if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
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*masked |= HAL_INT_RX;
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if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
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*masked |= HAL_INT_TX;
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/*
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* When doing RX interrupt mitigation, the RXOK bit is set
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* in AR_ISR even if the relevant bit in AR_IMR is clear.
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* Since this interrupt may be due to another source, don't
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* just automatically set HAL_INT_RX if it's set, otherwise
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* we could prematurely service the RX queue.
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*
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* In some cases, the driver can even handle all the RX
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* frames just before the mitigation interrupt fires.
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* The subsequent RX processing trip will then end up
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* processing 0 frames.
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*/
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#ifdef AH_AR5416_INTERRUPT_MITIGATION
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if (isr & AR_ISR_RXERR)
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*masked |= HAL_INT_RX;
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#else
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if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
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*masked |= HAL_INT_RX;
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#endif
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if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
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AR_ISR_TXEOL)) {
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*masked |= HAL_INT_TX;
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isr0 = OS_REG_READ(ah, AR_ISR_S0);
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OS_REG_WRITE(ah, AR_ISR_S0, isr0);
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isr1 = OS_REG_READ(ah, AR_ISR_S1);
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OS_REG_WRITE(ah, AR_ISR_S1, isr1);
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/*
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* Don't clear the primary ISR TX bits, clear
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* what causes them (S0/S1.)
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*/
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isr &= ~(AR_ISR_TXOK | AR_ISR_TXDESC |
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AR_ISR_TXERR | AR_ISR_TXEOL);
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ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK);
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ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC);
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ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR);
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ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL);
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}
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if ((isr & AR_ISR_GENTMR) || (! pCap->halAutoSleepSupport)) {
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uint32_t isr5;
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isr5 = OS_REG_READ(ah, AR_ISR_S5);
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OS_REG_WRITE(ah, AR_ISR_S5, isr5);
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isr &= ~AR_ISR_GENTMR;
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if (! pCap->halAutoSleepSupport)
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if (isr5 & AR_ISR_S5_TIM_TIMER)
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*masked |= HAL_INT_TIM_TIMER;
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}
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*masked |= mask2;
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}
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/*
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* Since we're not using AR_ISR_RAC, clear the status bits
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* for handled interrupts here. For bits whose interrupt
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* source is a secondary register, those bits should've been
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* masked out - instead of those bits being written back,
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* their source (ie, the secondary status registers) should
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* be cleared. That way there are no race conditions with
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* new triggers coming in whilst they've been read/cleared.
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*/
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OS_REG_WRITE(ah, AR_ISR, isr);
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/* Flush previous write */
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OS_REG_READ(ah, AR_ISR);
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if (AR_SREV_HOWL(ah))
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return AH_TRUE;
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if (sync_cause != 0) {
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if (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) {
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*masked |= HAL_INT_FATAL;
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}
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if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RADM CPL timeout\n",
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__func__);
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OS_REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
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OS_REG_WRITE(ah, AR_RC, 0);
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*masked |= HAL_INT_FATAL;
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}
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/*
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* On fatal errors collect ISR state for debugging.
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*/
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if (*masked & HAL_INT_FATAL) {
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AH_PRIVATE(ah)->ah_fatalState[0] = isr;
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AH_PRIVATE(ah)->ah_fatalState[1] = sync_cause;
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: fatal error, ISR_RAC 0x%x SYNC_CAUSE 0x%x\n",
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__func__, isr, sync_cause);
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}
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OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
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/* NB: flush write */
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(void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
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}
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return AH_TRUE;
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}
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/*
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* Atomically enables NIC interrupts. Interrupts are passed in
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* via the enumerated bitmask in ints.
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*/
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HAL_INT
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ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
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{
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struct ath_hal_5212 *ahp = AH5212(ah);
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uint32_t omask = ahp->ah_maskReg;
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uint32_t mask, mask2;
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HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n",
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__func__, omask, ints);
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if (omask & HAL_INT_GLOBAL) {
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HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__);
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OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
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(void) OS_REG_READ(ah, AR_IER);
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if (! AR_SREV_HOWL(ah)) {
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OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
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(void) OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE);
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OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
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(void) OS_REG_READ(ah, AR_INTR_SYNC_ENABLE);
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}
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}
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mask = ints & HAL_INT_COMMON;
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mask2 = 0;
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#ifdef AH_AR5416_INTERRUPT_MITIGATION
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/*
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* Overwrite default mask if Interrupt mitigation
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* is specified for AR5416
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*/
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if (ints & HAL_INT_RX)
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mask |= AR_IMR_RXERR | AR_IMR_RXMINTR | AR_IMR_RXINTM;
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#else
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if (ints & HAL_INT_RX)
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mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC;
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#endif
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if (ints & HAL_INT_TX) {
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if (ahp->ah_txOkInterruptMask)
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mask |= AR_IMR_TXOK;
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if (ahp->ah_txErrInterruptMask)
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mask |= AR_IMR_TXERR;
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if (ahp->ah_txDescInterruptMask)
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mask |= AR_IMR_TXDESC;
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if (ahp->ah_txEolInterruptMask)
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mask |= AR_IMR_TXEOL;
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}
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if (ints & (HAL_INT_BMISC)) {
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mask |= AR_IMR_BCNMISC;
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if (ints & HAL_INT_TIM)
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mask2 |= AR_IMR_S2_TIM;
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if (ints & HAL_INT_DTIM)
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mask2 |= AR_IMR_S2_DTIM;
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if (ints & HAL_INT_DTIMSYNC)
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mask2 |= AR_IMR_S2_DTIMSYNC;
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if (ints & HAL_INT_CABEND)
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mask2 |= (AR_IMR_S2_CABEND );
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if (ints & HAL_INT_CST)
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mask2 |= AR_IMR_S2_CST;
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if (ints & HAL_INT_TSFOOR)
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mask2 |= AR_IMR_S2_TSFOOR;
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}
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if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
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mask |= AR_IMR_BCNMISC;
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if (ints & HAL_INT_GTT)
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mask2 |= AR_IMR_S2_GTT;
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if (ints & HAL_INT_CST)
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mask2 |= AR_IMR_S2_CST;
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}
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/* Write the new IMR and store off our SW copy. */
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HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
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OS_REG_WRITE(ah, AR_IMR, mask);
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mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
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AR_IMR_S2_DTIM |
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AR_IMR_S2_DTIMSYNC |
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AR_IMR_S2_CABEND |
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AR_IMR_S2_CABTO |
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AR_IMR_S2_TSFOOR |
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AR_IMR_S2_GTT |
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AR_IMR_S2_CST);
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OS_REG_WRITE(ah, AR_IMR_S2, mask | mask2);
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ahp->ah_maskReg = ints;
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/* Re-enable interrupts if they were enabled before. */
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if (ints & HAL_INT_GLOBAL) {
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HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__);
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OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
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if (! AR_SREV_HOWL(ah)) {
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mask = AR_INTR_MAC_IRQ;
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if (ints & HAL_INT_GPIO)
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mask |= SM(AH5416(ah)->ah_gpioMask,
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AR_INTR_ASYNC_MASK_GPIO);
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OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, mask);
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OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, mask);
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mask = AR_INTR_SYNC_DEFAULT;
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if (ints & HAL_INT_GPIO)
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mask |= SM(AH5416(ah)->ah_gpioMask,
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AR_INTR_SYNC_MASK_GPIO);
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OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, mask);
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OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, mask);
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}
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}
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return omask;
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}
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