Alexander Motin 017cb944b1 Increment td->td_intr_nesting_level for LAPIC timer interrupts. Among other ... things it hints SCHED_ULE to run clock swi handlers on their native CPUs, avoiding many unneeded IPI_PREEMPT calls.		2010-07-24 10:49:59 +00:00
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bios
cpufreq	Core i5, same as previously Core2Duo, found to not set P-state for single	2010-06-19 13:09:42 +00:00
isa	Fix several un-/signedness bugs of r210290 and r210293. Add one more check.	2010-07-20 15:48:29 +00:00
x86	Increment td->td_intr_nesting_level for LAPIC timer interrupts. Among other	2010-07-24 10:49:59 +00:00