135 lines
6.2 KiB
C
135 lines
6.2 KiB
C
/*-
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* Copyright (c) 2000 Tsubai Masanari. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $NetBSD: hid.h,v 1.2 2001/08/22 21:05:25 matt Exp $
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* $FreeBSD$
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*/
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#ifndef _POWERPC_HID_H_
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#define _POWERPC_HID_H_
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/* Hardware Implementation Dependent registers for the PowerPC */
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#define HID0_EMCP 0x80000000 /* Enable MCP */
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#define HID0_DBP 0x40000000 /* Disable 60x bus parity generation */
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#define HID0_EBA 0x20000000 /* Enable 60x bus address parity checking */
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#define HID0_EBD 0x10000000 /* Enable 60x bus data parity checking */
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#define HID0_BCLK 0x08000000 /* CLK_OUT clock type selection */
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#define HID0_EICE 0x04000000 /* Enable ICE output */
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#define HID0_TBEN 0x04000000 /* Time base enable (7450) */
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#define HID0_ECLK 0x02000000 /* CLK_OUT clock type selection */
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#define HID0_PAR 0x01000000 /* Disable precharge of ARTRY */
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#define HID0_STEN 0x01000000 /* Software table search enable (7450) */
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#define HID0_HBATEN 0x00800000 /* High BAT enable (7457) */
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#define HID0_DOZE 0x00800000 /* Enable doze mode */
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#define HID0_NAP 0x00400000 /* Enable nap mode */
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#define HID0_SLEEP 0x00200000 /* Enable sleep mode */
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#define HID0_DPM 0x00100000 /* Enable Dynamic power management */
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#define HID0_RISEG 0x00080000 /* Read I-SEG */
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#define HID0_BHTCLR 0x00080000 /* Clear branch history table (7450) */
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#define HID0_EIEC 0x00040000 /* Enable internal error checking */
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#define HID0_XAEN 0x00040000 /* Enable eXtended Addressing (7450) */
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#define HID0_NHR 0x00010000 /* Not hard reset */
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#define HID0_ICE 0x00008000 /* Enable i-cache */
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#define HID0_DCE 0x00004000 /* Enable d-cache */
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#define HID0_ILOCK 0x00002000 /* i-cache lock */
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#define HID0_DLOCK 0x00001000 /* d-cache lock */
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#define HID0_ICFI 0x00000800 /* i-cache flush invalidate */
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#define HID0_DCFI 0x00000400 /* d-cache flush invalidate */
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#define HID0_SPD 0x00000200 /* Disable speculative cache access */
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#define HID0_XBSEN 0x00000100 /* Extended BAT block-size enable (7457) */
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#define HID0_IFEM 0x00000100 /* Enable M-bit for I-fetch */
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#define HID0_SGE 0x00000080 /* Enable store gathering */
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#define HID0_DCFA 0x00000040 /* Data cache flush assist */
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#define HID0_BTIC 0x00000020 /* Enable BTIC */
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#define HID0_ABE 0x00000008 /* Enable address broadcast */
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#define HID0_BHT 0x00000004 /* Enable branch history table */
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#define HID0_NOPTI 0x00000001 /* No-op the dcbt(st) */
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#define HID0_BITMASK \
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"\20" \
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"\040EMCP\037DBP\036EBA\035EBD\034BCLK\033EICE\032ECLK\031PAR" \
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"\030DOZE\027NAP\026SLEEP\025DPM\024RISEG\023EIEC\022res\021NHR" \
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"\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011IFEM" \
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"\010SGE\007DCFA\006BTIC\005FBIOB\004ABE\003BHT\002NOPDST\001NOPTI"
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#define HID0_7450_BITMASK \
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"\20" \
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"\040EMCP\037b1\036b2\035b3\034b4\033TBEN\032b6\031STEN" \
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"\030HBATEN\027NAP\026SLEEP\025DPM\024b12\023BHTCLR\022XAEN\021NHR" \
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"\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011XBSEN" \
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"\010SGE\007b25\006BTIC\005LRSTK\004FOLD\003BHT\002NOPDST\001NOPTI"
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/*
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* HID0 bit definitions per cpu model
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*
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* bit 603 604 750 7400 7410 7450 7457
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* 0 EMCP EMCP EMCP EMCP EMCP - -
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* 1 - ECP DBP - - - -
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* 2 EBA EBA EBA EBA EDA - -
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* 3 EBD EBD EBD EBD EBD - -
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* 4 SBCLK - BCLK BCKL BCLK - -
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* 5 EICE - - - - TBEN TBEN
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* 6 ECLK - ECLK ECLK ECLK - -
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* 7 PAR PAR PAR PAR PAR STEN STEN
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* 8 DOZE - DOZE DOZE DOZE - HBATEN
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* 9 NAP - NAP NAP NAP NAP NAP
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* 10 SLEEP - SLEEP SLEEP SLEEP SLEEP SLEEP
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* 11 DPM - DPM DPM DPM DPM DPM
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* 12 RISEG - - RISEG - - -
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* 13 - - - EIEC EIEC BHTCLR BHTCLR
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* 14 - - - - - XAEN XAEN
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* 15 - NHR NHR NHR NHR NHR NHR
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* 16 ICE ICE ICE ICE ICE ICE ICE
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* 17 DCE DCE DCE DCE DCE DCE DCE
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* 18 ILOCK ILOCK ILOCK ILOCK ILOCK ILOCK ILOCK
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* 19 DLOCK DLOCK DLOCK DLOCK DLOCK DLOCK DLOCK
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* 20 ICFI ICFI ICFI ICFI ICFI ICFI ICFI
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* 21 DCFI DCFI DCFI DCFI DCFI DCFI DCFI
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* 22 - - SPD SPD SPG SPD SPD
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* 23 - - IFEM IFTT IFTT - XBSEN
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* 24 - SIE SGE SGE SGE SGE SGE
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* 25 - - DCFA DCFA DCFA - -
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* 26 - - BTIC BTIC BTIC BTIC BTIC
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* 27 FBIOB - - - - LRSTK LRSTK
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* 28 - - ABE - - FOLD FOLD
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* 29 - BHT BHT BHT BHT BHT BHT
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* 30 - - - NOPDST NOPDST NOPDST NOPDST
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* 31 NOOPTI - NOOPTI NOPTI NOPTI NOPTI NOPTI
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*
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* 604: ECP = Enable cache parity checking
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* 604: SIE = Serial instruction execution disable
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* 7450: TBEN = Time Base Enable
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* 7450: STEN = Software table lookup enable
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* 7450: BHTCLR = Branch history clear
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* 7450: XAEN = Extended Addressing Enabled
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* 7450: LRSTK = Link Register Stack Enable
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* 7450: FOLD = Branch folding enable
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* 7457: HBATEN = High BAT Enable
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* 7457: XBSEN = Extended BAT Block Size Enable
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*/
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#endif /* _POWERPC_HID_H_ */
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