2f03a95fd2
- Do not explicitly count active descriptors. It allows hardware reset to happen while device is still referenced, plus simplifies locking. - Do not stop/start callout each time the queue becomes empty. Let it run to completion and rearm if needed, that is much cheaper then to touch it every time, plus also simplifies locking. - Decouple submit and cleanup locks, making driver reentrant. - Avoid memory mapped status register read on every interrupt. - Improve locking during device attach/detach. - Remove some no longer used variables. Reviewed by: cem MFC after: 1 week Sponsored by: iXsystems, Inc. Differential Revision: https://reviews.freebsd.org/D19231
602 lines
15 KiB
C
602 lines
15 KiB
C
/*-
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* Copyright (C) 2012 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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__FBSDID("$FreeBSD$");
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#ifndef __IOAT_INTERNAL_H__
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#define __IOAT_INTERNAL_H__
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#include <sys/_task.h>
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#define DEVICE2SOFTC(dev) ((struct ioat_softc *) device_get_softc(dev))
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#define KTR_IOAT KTR_SPARE3
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#define ioat_read_chancnt(ioat) \
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ioat_read_1((ioat), IOAT_CHANCNT_OFFSET)
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#define ioat_read_xfercap(ioat) \
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(ioat_read_1((ioat), IOAT_XFERCAP_OFFSET) & IOAT_XFERCAP_VALID_MASK)
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#define ioat_write_intrctrl(ioat, value) \
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ioat_write_1((ioat), IOAT_INTRCTRL_OFFSET, (value))
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#define ioat_read_cbver(ioat) \
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(ioat_read_1((ioat), IOAT_CBVER_OFFSET) & 0xFF)
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#define ioat_read_dmacapability(ioat) \
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ioat_read_4((ioat), IOAT_DMACAPABILITY_OFFSET)
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#define ioat_write_chanctrl(ioat, value) \
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ioat_write_2((ioat), IOAT_CHANCTRL_OFFSET, (value))
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static __inline uint64_t
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ioat_bus_space_read_8_lower_first(bus_space_tag_t tag,
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bus_space_handle_t handle, bus_size_t offset)
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{
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return (bus_space_read_4(tag, handle, offset) |
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((uint64_t)bus_space_read_4(tag, handle, offset + 4)) << 32);
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}
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static __inline void
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ioat_bus_space_write_8_lower_first(bus_space_tag_t tag,
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bus_space_handle_t handle, bus_size_t offset, uint64_t val)
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{
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bus_space_write_4(tag, handle, offset, val);
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bus_space_write_4(tag, handle, offset + 4, val >> 32);
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}
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#ifdef __i386__
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#define ioat_bus_space_read_8 ioat_bus_space_read_8_lower_first
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#define ioat_bus_space_write_8 ioat_bus_space_write_8_lower_first
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#else
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#define ioat_bus_space_read_8(tag, handle, offset) \
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bus_space_read_8((tag), (handle), (offset))
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#define ioat_bus_space_write_8(tag, handle, offset, val) \
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bus_space_write_8((tag), (handle), (offset), (val))
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#endif
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#define ioat_read_1(ioat, offset) \
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bus_space_read_1((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
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(offset))
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#define ioat_read_2(ioat, offset) \
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bus_space_read_2((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
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(offset))
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#define ioat_read_4(ioat, offset) \
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bus_space_read_4((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
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(offset))
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#define ioat_read_8(ioat, offset) \
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ioat_bus_space_read_8((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
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(offset))
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#define ioat_read_double_4(ioat, offset) \
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ioat_bus_space_read_8_lower_first((ioat)->pci_bus_tag, \
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(ioat)->pci_bus_handle, (offset))
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#define ioat_write_1(ioat, offset, value) \
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bus_space_write_1((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
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(offset), (value))
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#define ioat_write_2(ioat, offset, value) \
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bus_space_write_2((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
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(offset), (value))
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#define ioat_write_4(ioat, offset, value) \
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bus_space_write_4((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
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(offset), (value))
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#define ioat_write_8(ioat, offset, value) \
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ioat_bus_space_write_8((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
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(offset), (value))
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#define ioat_write_double_4(ioat, offset, value) \
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ioat_bus_space_write_8_lower_first((ioat)->pci_bus_tag, \
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(ioat)->pci_bus_handle, (offset), (value))
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MALLOC_DECLARE(M_IOAT);
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SYSCTL_DECL(_hw_ioat);
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extern int g_ioat_debug_level;
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struct generic_dma_control {
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uint32_t int_enable:1;
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uint32_t src_snoop_disable:1;
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uint32_t dest_snoop_disable:1;
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uint32_t completion_update:1;
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uint32_t fence:1;
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uint32_t reserved1:1;
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uint32_t src_page_break:1;
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uint32_t dest_page_break:1;
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uint32_t bundle:1;
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uint32_t dest_dca:1;
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uint32_t hint:1;
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uint32_t reserved2:13;
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uint32_t op:8;
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};
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struct ioat_generic_hw_descriptor {
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uint32_t size;
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union {
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uint32_t control_raw;
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struct generic_dma_control control_generic;
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} u;
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uint64_t src_addr;
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uint64_t dest_addr;
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uint64_t next;
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uint64_t reserved[4];
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};
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struct ioat_dma_hw_descriptor {
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uint32_t size;
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union {
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uint32_t control_raw;
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struct generic_dma_control control_generic;
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struct {
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uint32_t int_enable:1;
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uint32_t src_snoop_disable:1;
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uint32_t dest_snoop_disable:1;
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uint32_t completion_update:1;
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uint32_t fence:1;
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uint32_t null:1;
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uint32_t src_page_break:1;
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uint32_t dest_page_break:1;
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uint32_t bundle:1;
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uint32_t dest_dca:1;
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uint32_t hint:1;
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uint32_t reserved:13;
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#define IOAT_OP_COPY 0x00
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uint32_t op:8;
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} control;
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} u;
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uint64_t src_addr;
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uint64_t dest_addr;
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uint64_t next;
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uint64_t next_src_addr;
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uint64_t next_dest_addr;
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uint64_t user1;
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uint64_t user2;
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};
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struct ioat_fill_hw_descriptor {
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uint32_t size;
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union {
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uint32_t control_raw;
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struct generic_dma_control control_generic;
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struct {
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uint32_t int_enable:1;
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uint32_t reserved:1;
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uint32_t dest_snoop_disable:1;
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uint32_t completion_update:1;
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uint32_t fence:1;
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uint32_t reserved2:2;
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uint32_t dest_page_break:1;
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uint32_t bundle:1;
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uint32_t reserved3:15;
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#define IOAT_OP_FILL 0x01
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uint32_t op:8;
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} control;
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} u;
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uint64_t src_data;
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uint64_t dest_addr;
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uint64_t next;
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uint64_t reserved;
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uint64_t next_dest_addr;
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uint64_t user1;
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uint64_t user2;
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};
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struct ioat_crc32_hw_descriptor {
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uint32_t size;
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union {
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uint32_t control_raw;
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struct generic_dma_control control_generic;
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struct {
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uint32_t int_enable:1;
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uint32_t src_snoop_disable:1;
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uint32_t dest_snoop_disable:1;
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uint32_t completion_update:1;
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uint32_t fence:1;
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uint32_t reserved1:3;
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uint32_t bundle:1;
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uint32_t dest_dca:1;
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uint32_t hint:1;
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uint32_t use_seed:1;
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/*
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* crc_location:
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* For IOAT_OP_MOVECRC_TEST and IOAT_OP_CRC_TEST:
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* 0: comparison value is pointed to by CRC Address
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* field.
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* 1: comparison value follows data in wire format
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* ("inverted reflected bit order") in the 4 bytes
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* following the source data.
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*
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* For IOAT_OP_CRC_STORE:
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* 0: Result will be stored at location pointed to by
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* CRC Address field (in wire format).
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* 1: Result will be stored directly following the
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* source data.
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*
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* For IOAT_OP_MOVECRC_STORE:
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* 0: Result will be stored at location pointed to by
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* CRC Address field (in wire format).
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* 1: Result will be stored directly following the
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* *destination* data.
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*/
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uint32_t crc_location:1;
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uint32_t reserved2:11;
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/*
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* MOVECRC - Move data in the same way as standard copy
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* operation, but also compute CRC32.
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*
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* CRC - Only compute CRC on source data.
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*
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* There is a CRC accumulator register in the hardware.
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* If 'initial' is set, it is initialized to the value
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* in 'seed.'
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*
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* In all modes, these operators accumulate size bytes
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* at src_addr into the running CRC32C.
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*
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* Store mode emits the accumulated CRC, in wire
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* format, as specified by the crc_location bit above.
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*
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* Test mode compares the accumulated CRC against the
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* reference CRC, as described in crc_location above.
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* On failure, halts the DMA engine with a CRC error
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* status.
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*/
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#define IOAT_OP_MOVECRC 0x41
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#define IOAT_OP_MOVECRC_TEST 0x42
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#define IOAT_OP_MOVECRC_STORE 0x43
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#define IOAT_OP_CRC 0x81
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#define IOAT_OP_CRC_TEST 0x82
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#define IOAT_OP_CRC_STORE 0x83
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uint32_t op:8;
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} control;
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} u;
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uint64_t src_addr;
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uint64_t dest_addr;
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uint64_t next;
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uint64_t next_src_addr;
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uint64_t next_dest_addr;
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uint32_t seed;
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uint32_t reserved;
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uint64_t crc_address;
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};
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struct ioat_xor_hw_descriptor {
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uint32_t size;
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union {
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uint32_t control_raw;
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struct generic_dma_control control_generic;
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struct {
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uint32_t int_enable:1;
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uint32_t src_snoop_disable:1;
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uint32_t dest_snoop_disable:1;
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uint32_t completion_update:1;
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uint32_t fence:1;
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uint32_t src_count:3;
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uint32_t bundle:1;
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uint32_t dest_dca:1;
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uint32_t hint:1;
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uint32_t reserved:13;
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#define IOAT_OP_XOR 0x87
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#define IOAT_OP_XOR_VAL 0x88
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uint32_t op:8;
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} control;
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} u;
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uint64_t src_addr;
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uint64_t dest_addr;
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uint64_t next;
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uint64_t src_addr2;
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uint64_t src_addr3;
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uint64_t src_addr4;
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uint64_t src_addr5;
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};
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struct ioat_xor_ext_hw_descriptor {
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uint64_t src_addr6;
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uint64_t src_addr7;
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uint64_t src_addr8;
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uint64_t next;
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uint64_t reserved[4];
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};
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struct ioat_pq_hw_descriptor {
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uint32_t size;
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union {
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uint32_t control_raw;
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struct generic_dma_control control_generic;
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struct {
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uint32_t int_enable:1;
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uint32_t src_snoop_disable:1;
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uint32_t dest_snoop_disable:1;
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uint32_t completion_update:1;
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uint32_t fence:1;
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uint32_t src_count:3;
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uint32_t bundle:1;
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uint32_t dest_dca:1;
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uint32_t hint:1;
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uint32_t p_disable:1;
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uint32_t q_disable:1;
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uint32_t reserved:11;
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#define IOAT_OP_PQ 0x89
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#define IOAT_OP_PQ_VAL 0x8a
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uint32_t op:8;
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} control;
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} u;
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uint64_t src_addr;
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uint64_t p_addr;
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uint64_t next;
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uint64_t src_addr2;
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uint64_t src_addr3;
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uint8_t coef[8];
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uint64_t q_addr;
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};
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struct ioat_pq_ext_hw_descriptor {
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uint64_t src_addr4;
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uint64_t src_addr5;
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uint64_t src_addr6;
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uint64_t next;
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uint64_t src_addr7;
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uint64_t src_addr8;
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uint64_t reserved[2];
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};
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struct ioat_pq_update_hw_descriptor {
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uint32_t size;
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union {
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uint32_t control_raw;
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struct generic_dma_control control_generic;
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struct {
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uint32_t int_enable:1;
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uint32_t src_snoop_disable:1;
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uint32_t dest_snoop_disable:1;
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uint32_t completion_update:1;
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uint32_t fence:1;
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uint32_t src_cnt:3;
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uint32_t bundle:1;
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uint32_t dest_dca:1;
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uint32_t hint:1;
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uint32_t p_disable:1;
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uint32_t q_disable:1;
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uint32_t reserved:3;
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uint32_t coef:8;
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#define IOAT_OP_PQ_UP 0x8b
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uint32_t op:8;
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} control;
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} u;
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uint64_t src_addr;
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uint64_t p_addr;
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uint64_t next;
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uint64_t src_addr2;
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uint64_t p_src;
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uint64_t q_src;
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uint64_t q_addr;
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};
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struct ioat_raw_hw_descriptor {
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uint64_t field[8];
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};
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struct bus_dmadesc {
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bus_dmaengine_callback_t callback_fn;
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void *callback_arg;
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};
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struct ioat_descriptor {
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struct bus_dmadesc bus_dmadesc;
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uint32_t id;
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};
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/* Unused by this driver at this time. */
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#define IOAT_OP_MARKER 0x84
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/*
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* Deprecated OPs -- v3 DMA generates an abort if given these. And this driver
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* doesn't support anything older than v3.
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*/
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#define IOAT_OP_OLD_XOR 0x85
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#define IOAT_OP_OLD_XOR_VAL 0x86
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/* One of these per allocated PCI device. */
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struct ioat_softc {
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bus_dmaengine_t dmaengine;
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#define to_ioat_softc(_dmaeng) \
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({ \
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bus_dmaengine_t *_p = (_dmaeng); \
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(struct ioat_softc *)((char *)_p - \
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offsetof(struct ioat_softc, dmaengine)); \
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})
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device_t device;
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int version;
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unsigned chan_idx;
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bus_space_tag_t pci_bus_tag;
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bus_space_handle_t pci_bus_handle;
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struct resource *pci_resource;
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int pci_resource_id;
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uint32_t max_xfer_size;
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uint32_t capabilities;
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uint32_t ring_size_order;
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uint16_t intrdelay_max;
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uint16_t cached_intrdelay;
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int rid;
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struct resource *res;
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void *tag;
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bus_dma_tag_t hw_desc_tag;
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bus_dmamap_t hw_desc_map;
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bus_dma_tag_t comp_update_tag;
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bus_dmamap_t comp_update_map;
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uint64_t *comp_update;
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bus_addr_t comp_update_bus_addr;
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boolean_t quiescing;
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boolean_t destroying;
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boolean_t is_submitter_processing;
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boolean_t intrdelay_supported;
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boolean_t resetting; /* submit_lock */
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boolean_t resetting_cleanup; /* cleanup_lock */
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struct ioat_descriptor *ring;
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union ioat_hw_descriptor {
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struct ioat_generic_hw_descriptor generic;
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struct ioat_dma_hw_descriptor dma;
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struct ioat_fill_hw_descriptor fill;
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struct ioat_crc32_hw_descriptor crc32;
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struct ioat_xor_hw_descriptor xor;
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struct ioat_xor_ext_hw_descriptor xor_ext;
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struct ioat_pq_hw_descriptor pq;
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struct ioat_pq_ext_hw_descriptor pq_ext;
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struct ioat_raw_hw_descriptor raw;
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} *hw_desc_ring;
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|
bus_addr_t hw_desc_bus_addr;
|
|
#define RING_PHYS_ADDR(sc, i) (sc)->hw_desc_bus_addr + \
|
|
(((i) % (1 << (sc)->ring_size_order)) * sizeof(struct ioat_dma_hw_descriptor))
|
|
|
|
struct mtx_padalign submit_lock;
|
|
struct callout poll_timer;
|
|
struct task reset_task;
|
|
struct mtx_padalign cleanup_lock;
|
|
|
|
uint32_t refcnt;
|
|
uint32_t head;
|
|
uint32_t acq_head;
|
|
uint32_t tail;
|
|
bus_addr_t last_seen;
|
|
|
|
struct {
|
|
uint64_t interrupts;
|
|
uint64_t descriptors_processed;
|
|
uint64_t descriptors_error;
|
|
uint64_t descriptors_submitted;
|
|
|
|
uint32_t channel_halts;
|
|
uint32_t last_halt_chanerr;
|
|
} stats;
|
|
};
|
|
|
|
void ioat_test_attach(void);
|
|
void ioat_test_detach(void);
|
|
|
|
/*
|
|
* XXX DO NOT USE this routine for obtaining the current completed descriptor.
|
|
*
|
|
* The double_4 read on ioat<3.3 appears to result in torn reads. And v3.2
|
|
* hardware is still commonplace (Broadwell Xeon has it). Instead, use the
|
|
* device-pushed *comp_update.
|
|
*
|
|
* It is safe to use ioat_get_chansts() for the low status bits.
|
|
*/
|
|
static inline uint64_t
|
|
ioat_get_chansts(struct ioat_softc *ioat)
|
|
{
|
|
uint64_t status;
|
|
|
|
if (ioat->version >= IOAT_VER_3_3)
|
|
status = ioat_read_8(ioat, IOAT_CHANSTS_OFFSET);
|
|
else
|
|
/* Must read lower 4 bytes before upper 4 bytes. */
|
|
status = ioat_read_double_4(ioat, IOAT_CHANSTS_OFFSET);
|
|
return (status);
|
|
}
|
|
|
|
static inline void
|
|
ioat_write_chancmp(struct ioat_softc *ioat, uint64_t addr)
|
|
{
|
|
|
|
if (ioat->version >= IOAT_VER_3_3)
|
|
ioat_write_8(ioat, IOAT_CHANCMP_OFFSET_LOW, addr);
|
|
else
|
|
ioat_write_double_4(ioat, IOAT_CHANCMP_OFFSET_LOW, addr);
|
|
}
|
|
|
|
static inline void
|
|
ioat_write_chainaddr(struct ioat_softc *ioat, uint64_t addr)
|
|
{
|
|
|
|
if (ioat->version >= IOAT_VER_3_3)
|
|
ioat_write_8(ioat, IOAT_CHAINADDR_OFFSET_LOW, addr);
|
|
else
|
|
ioat_write_double_4(ioat, IOAT_CHAINADDR_OFFSET_LOW, addr);
|
|
}
|
|
|
|
static inline boolean_t
|
|
is_ioat_active(uint64_t status)
|
|
{
|
|
return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
|
|
}
|
|
|
|
static inline boolean_t
|
|
is_ioat_idle(uint64_t status)
|
|
{
|
|
return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_IDLE);
|
|
}
|
|
|
|
static inline boolean_t
|
|
is_ioat_halted(uint64_t status)
|
|
{
|
|
return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
|
|
}
|
|
|
|
static inline boolean_t
|
|
is_ioat_suspended(uint64_t status)
|
|
{
|
|
return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
|
|
}
|
|
|
|
static inline void
|
|
ioat_suspend(struct ioat_softc *ioat)
|
|
{
|
|
ioat_write_1(ioat, IOAT_CHANCMD_OFFSET, IOAT_CHANCMD_SUSPEND);
|
|
}
|
|
|
|
static inline void
|
|
ioat_reset(struct ioat_softc *ioat)
|
|
{
|
|
ioat_write_1(ioat, IOAT_CHANCMD_OFFSET, IOAT_CHANCMD_RESET);
|
|
}
|
|
|
|
static inline boolean_t
|
|
ioat_reset_pending(struct ioat_softc *ioat)
|
|
{
|
|
uint8_t cmd;
|
|
|
|
cmd = ioat_read_1(ioat, IOAT_CHANCMD_OFFSET);
|
|
return ((cmd & IOAT_CHANCMD_RESET) != 0);
|
|
}
|
|
|
|
#endif /* __IOAT_INTERNAL_H__ */
|