e632b60f46
attachment code for various SOCs and busses. Remove all the static and should-have-been-static and named-differently instances of it. This should eliminate the recently-grown build warnings about multiple definitions when building arm kernels.
396 lines
11 KiB
C
396 lines
11 KiB
C
/*-
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* Copyright (c) 2014-2015 M. Warner Losh <imp@freebsd.org>
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* Copyright (c) 2015 Luiz Otavio O Souza <loos@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* The magic-bit-bang sequence used in this code may be based on a linux
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* platform driver in the Allwinner SDK from Allwinner Technology Co., Ltd.
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* www.allwinnertech.com, by Daniel Wang <danielwang@allwinnertech.com>
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* though none of the original code was copied.
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*/
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#include "opt_bus.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ahci/ahci.h>
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#include <dev/extres/clk/clk.h>
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/*
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* Allwinner a1x/a2x/a8x SATA attachment. This is just the AHCI register
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* set with a few extra implementation-specific registers that need to
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* be accounted for. There's only one PHY in the system, and it needs
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* to be trained to bring the link up. In addition, there's some DMA
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* specific things that need to be done as well. These things are also
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* just about completely undocumented, except in ugly code in the Linux
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* SDK Allwinner releases.
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*/
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/* BITx -- Unknown bit that needs to be set/cleared at position x */
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/* UFx -- Uknown multi-bit field frobbed during init */
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#define AHCI_BISTAFR 0x00A0
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#define AHCI_BISTCR 0x00A4
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#define AHCI_BISTFCTR 0x00A8
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#define AHCI_BISTSR 0x00AC
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#define AHCI_BISTDECR 0x00B0
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#define AHCI_DIAGNR 0x00B4
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#define AHCI_DIAGNR1 0x00B8
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#define AHCI_OOBR 0x00BC
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#define AHCI_PHYCS0R 0x00C0
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/* Bits 0..17 are a mystery */
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#define PHYCS0R_BIT18 (1 << 18)
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#define PHYCS0R_POWER_ENABLE (1 << 19)
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#define PHYCS0R_UF1_MASK (7 << 20) /* Unknown Field 1 */
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#define PHYCS0R_UF1_INIT (3 << 20)
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#define PHYCS0R_BIT23 (1 << 23)
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#define PHYCS0R_UF2_MASK (7 << 24) /* Uknown Field 2 */
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#define PHYCS0R_UF2_INIT (5 << 24)
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/* Bit 27 mystery */
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#define PHYCS0R_POWER_STATUS_MASK (7 << 28)
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#define PHYCS0R_PS_GOOD (2 << 28)
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/* Bit 31 mystery */
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#define AHCI_PHYCS1R 0x00C4
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/* Bits 0..5 are a mystery */
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#define PHYCS1R_UF1_MASK (3 << 6)
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#define PHYCS1R_UF1_INIT (2 << 6)
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#define PHYCS1R_UF2_MASK (0x1f << 8)
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#define PHYCS1R_UF2_INIT (6 << 8)
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/* Bits 13..14 are a mystery */
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#define PHYCS1R_BIT15 (1 << 15)
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#define PHYCS1R_UF3_MASK (3 << 16)
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#define PHYCS1R_UF3_INIT (2 << 16)
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/* Bit 18 mystery */
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#define PHYCS1R_HIGHZ (1 << 19)
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/* Bits 20..27 mystery */
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#define PHYCS1R_BIT28 (1 << 28)
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/* Bits 29..31 mystery */
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#define AHCI_PHYCS2R 0x00C8
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/* bits 0..4 mystery */
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#define PHYCS2R_UF1_MASK (0x1f << 5)
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#define PHYCS2R_UF1_INIT (0x19 << 5)
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/* Bits 10..23 mystery */
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#define PHYCS2R_CALIBRATE (1 << 24)
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/* Bits 25..31 mystery */
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#define AHCI_TIMER1MS 0x00E0
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#define AHCI_GPARAM1R 0x00E8
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#define AHCI_GPARAM2R 0x00EC
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#define AHCI_PPARAMR 0x00F0
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#define AHCI_TESTR 0x00F4
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#define AHCI_VERSIONR 0x00F8
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#define AHCI_IDR 0x00FC
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#define AHCI_RWCR 0x00FC
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#define AHCI_P0DMACR 0x0070
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#define AHCI_P0PHYCR 0x0078
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#define AHCI_P0PHYSR 0x007C
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#define PLL_FREQ 100000000
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static void inline
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ahci_set(struct resource *m, bus_size_t off, uint32_t set)
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{
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uint32_t val = ATA_INL(m, off);
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val |= set;
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ATA_OUTL(m, off, val);
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}
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static void inline
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ahci_clr(struct resource *m, bus_size_t off, uint32_t clr)
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{
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uint32_t val = ATA_INL(m, off);
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val &= ~clr;
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ATA_OUTL(m, off, val);
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}
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static void inline
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ahci_mask_set(struct resource *m, bus_size_t off, uint32_t mask, uint32_t set)
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{
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uint32_t val = ATA_INL(m, off);
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val &= mask;
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val |= set;
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ATA_OUTL(m, off, val);
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}
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/*
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* Should this be phy_reset or phy_init
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*/
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#define PHY_RESET_TIMEOUT 1000
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static void
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ahci_a10_phy_reset(device_t dev)
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{
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uint32_t to, val;
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struct ahci_controller *ctlr = device_get_softc(dev);
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/*
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* Here starts the magic -- most of the comments are based
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* on guesswork, names of routines and printf error
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* messages. The code works, but it will do that even if the
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* comments are 100% BS.
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*/
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/*
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* Lock out other access while we initialize. Or at least that
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* seems to be the case based on Linux SDK #defines. Maybe this
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* put things into reset?
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*/
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ATA_OUTL(ctlr->r_mem, AHCI_RWCR, 0);
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DELAY(100);
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/*
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* Set bit 19 in PHYCS1R. Guessing this disables driving the PHY
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* port for a bit while we reset things.
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*/
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ahci_set(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_HIGHZ);
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/*
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* Frob PHYCS0R...
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*/
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ahci_mask_set(ctlr->r_mem, AHCI_PHYCS0R,
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~PHYCS0R_UF2_MASK,
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PHYCS0R_UF2_INIT | PHYCS0R_BIT23 | PHYCS0R_BIT18);
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/*
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* Set three fields in PHYCS1R
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*/
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ahci_mask_set(ctlr->r_mem, AHCI_PHYCS1R,
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~(PHYCS1R_UF1_MASK | PHYCS1R_UF2_MASK | PHYCS1R_UF3_MASK),
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PHYCS1R_UF1_INIT | PHYCS1R_UF2_INIT | PHYCS1R_UF3_INIT);
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/*
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* Two more mystery bits in PHYCS1R. -- can these be combined above?
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*/
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ahci_set(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_BIT15 | PHYCS1R_BIT28);
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/*
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* Now clear that first mysery bit. Perhaps this starts
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* driving the PHY again so we can power it up and start
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* talking to the SATA drive, if any below.
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*/
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ahci_clr(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_HIGHZ);
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/*
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* Frob PHYCS0R again...
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*/
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ahci_mask_set(ctlr->r_mem, AHCI_PHYCS0R,
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~PHYCS0R_UF1_MASK, PHYCS0R_UF1_INIT);
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/*
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* Frob PHYCS2R, because 25 means something?
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*/
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ahci_mask_set(ctlr->r_mem, AHCI_PHYCS2R, ~PHYCS2R_UF1_MASK,
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PHYCS2R_UF1_INIT);
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DELAY(100); /* WAG */
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/*
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* Turn on the power to the PHY and wait for it to report back
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* good?
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*/
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ahci_set(ctlr->r_mem, AHCI_PHYCS0R, PHYCS0R_POWER_ENABLE);
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for (to = PHY_RESET_TIMEOUT; to > 0; to--) {
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val = ATA_INL(ctlr->r_mem, AHCI_PHYCS0R);
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if ((val & PHYCS0R_POWER_STATUS_MASK) == PHYCS0R_PS_GOOD)
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break;
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DELAY(10);
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}
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if (to == 0 && bootverbose)
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device_printf(dev, "PHY Power Failed PHYCS0R = %#x\n", val);
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/*
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* Calibrate the clocks between the device and the host. This appears
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* to be an automated process that clears the bit when it is done.
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*/
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ahci_set(ctlr->r_mem, AHCI_PHYCS2R, PHYCS2R_CALIBRATE);
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for (to = PHY_RESET_TIMEOUT; to > 0; to--) {
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val = ATA_INL(ctlr->r_mem, AHCI_PHYCS2R);
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if ((val & PHYCS2R_CALIBRATE) == 0)
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break;
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DELAY(10);
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}
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if (to == 0 && bootverbose)
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device_printf(dev, "PHY Cal Failed PHYCS2R %#x\n", val);
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/*
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* OK, let things settle down a bit.
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*/
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DELAY(1000);
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/*
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* Go back into normal mode now that we've calibrated the PHY.
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*/
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ATA_OUTL(ctlr->r_mem, AHCI_RWCR, 7);
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}
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static void
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ahci_a10_ch_start(struct ahci_channel *ch)
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{
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uint32_t reg;
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/*
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* Magical values from Allwinner SDK, setup the DMA before start
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* operations on this channel.
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*/
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reg = ATA_INL(ch->r_mem, AHCI_P0DMACR);
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reg &= ~0xff00;
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reg |= 0x4400;
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ATA_OUTL(ch->r_mem, AHCI_P0DMACR, reg);
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}
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static int
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ahci_a10_ctlr_reset(device_t dev)
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{
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ahci_a10_phy_reset(dev);
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return (ahci_ctlr_reset(dev));
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}
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static int
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ahci_a10_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-ahci"))
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return (ENXIO);
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device_set_desc(dev, "Allwinner Integrated AHCI controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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ahci_a10_attach(device_t dev)
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{
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int error;
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struct ahci_controller *ctlr;
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clk_t clk_pll, clk_gate;
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ctlr = device_get_softc(dev);
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clk_pll = clk_gate = NULL;
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ctlr->quirks = AHCI_Q_NOPMP;
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ctlr->vendorid = 0;
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ctlr->deviceid = 0;
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ctlr->subvendorid = 0;
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ctlr->subdeviceid = 0;
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ctlr->r_rid = 0;
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if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&ctlr->r_rid, RF_ACTIVE)))
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return (ENXIO);
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/* Enable clocks */
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error = clk_get_by_ofw_index(dev, 0, 0, &clk_pll);
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if (error != 0) {
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device_printf(dev, "Cannot get PLL clock\n");
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goto fail;
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}
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error = clk_get_by_ofw_index(dev, 0, 1, &clk_gate);
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if (error != 0) {
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device_printf(dev, "Cannot get gate clock\n");
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goto fail;
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}
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error = clk_set_freq(clk_pll, PLL_FREQ, CLK_SET_ROUND_DOWN);
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if (error != 0) {
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device_printf(dev, "Cannot set PLL frequency\n");
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goto fail;
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}
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error = clk_enable(clk_pll);
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if (error != 0) {
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device_printf(dev, "Cannot enable PLL\n");
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goto fail;
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}
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error = clk_enable(clk_gate);
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if (error != 0) {
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device_printf(dev, "Cannot enable clk gate\n");
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goto fail;
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}
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/* Reset controller */
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if ((error = ahci_a10_ctlr_reset(dev)) != 0)
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goto fail;
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/*
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* No MSI registers on this platform.
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*/
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ctlr->msi = 0;
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ctlr->numirqs = 1;
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/* Channel start callback(). */
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ctlr->ch_start = ahci_a10_ch_start;
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/*
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* Note: ahci_attach will release ctlr->r_mem on errors automatically
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*/
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return (ahci_attach(dev));
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fail:
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if (clk_gate != NULL)
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clk_release(clk_gate);
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if (clk_pll != NULL)
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clk_release(clk_pll);
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bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
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return (error);
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}
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static int
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ahci_a10_detach(device_t dev)
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{
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return (ahci_detach(dev));
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}
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static device_method_t ahci_ata_methods[] = {
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DEVMETHOD(device_probe, ahci_a10_probe),
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DEVMETHOD(device_attach, ahci_a10_attach),
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DEVMETHOD(device_detach, ahci_a10_detach),
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DEVMETHOD(bus_print_child, ahci_print_child),
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DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
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DEVMETHOD(bus_release_resource, ahci_release_resource),
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DEVMETHOD(bus_setup_intr, ahci_setup_intr),
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DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
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DEVMETHOD(bus_child_location_str, ahci_child_location_str),
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DEVMETHOD_END
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};
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static driver_t ahci_ata_driver = {
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"ahci",
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ahci_ata_methods,
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sizeof(struct ahci_controller)
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};
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DRIVER_MODULE(ahci, simplebus, ahci_ata_driver, ahci_devclass, 0, 0);
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