Adrian Chadd cdb59558b9 Begin implementing correct MIPS24K sampling mode behaviour. ... * Add the interrupt bit in the configuration register * Correctly set the counter register for the sampling overflow interrupt. The interrupt is asserted when bit 31 is set. So set the overflow value at 0x80000000 and subtract the programmed value as appropriate.		2011-10-07 06:13:38 +00:00
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hwpmc_amd.c
hwpmc_amd.h
hwpmc_arm.c
hwpmc_core.c
hwpmc_core.h
hwpmc_ia64.c
hwpmc_intel.c
hwpmc_logging.c
hwpmc_mips24k.c
hwpmc_mips24k.h	Begin implementing correct MIPS24K sampling mode behaviour.	2011-10-07 06:13:38 +00:00
hwpmc_mips.c
hwpmc_mod.c
hwpmc_pentium.c
hwpmc_pentium.h
hwpmc_piv.c
hwpmc_piv.h
hwpmc_powerpc.c
hwpmc_ppro.c
hwpmc_ppro.h
hwpmc_sparc64.c
hwpmc_tsc.c
hwpmc_tsc.h
hwpmc_uncore.c
hwpmc_uncore.h
hwpmc_x86.c
hwpmc_xscale.c
hwpmc_xscale.h
pmc_events.h