92ced03849
which prevents erroneous packets from being put onto the protocol stack; enhance error detection for B-channel HDLC errors; remove old cvs id´s.
263 lines
8.6 KiB
C
263 lines
8.6 KiB
C
/*
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* Copyright (c) 1999, 2000 Dave Boyce. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*---------------------------------------------------------------------------
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*
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* i4b_iwic - isdn4bsd Winbond W6692 driver
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* ----------------------------------------
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*
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* $FreeBSD$
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*
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* last edit-date: [Sun Jan 21 11:09:46 2001]
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*
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*---------------------------------------------------------------------------*/
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#ifndef _I4B_W6692_H_
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#define _I4B_W6692_H_
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#define IWIC_BCH_A 0 /* channel A */
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#define IWIC_BCH_B 1 /* channel B */
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/*---------------------------------------------------------------------------*
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* FIFO depths
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*---------------------------------------------------------------------------*/
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#define IWIC_DCHAN_FIFO_LEN 64
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#define IWIC_BCHAN_FIFO_LEN 64
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/*---------------------------------------------------------------------------*
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* D-Channel register offsets
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*---------------------------------------------------------------------------*/
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#define D_RFIFO 0x00 /* D channel receive FIFO */
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#define D_XFIFO 0x04 /* D channel transmit FIFO */
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#define D_CMDR 0x08 /* D channel command register */
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#define D_MODE 0x0c /* D channel mode control */
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#define D_TIMR 0x10 /* D channel timer control */
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#define D_EXIR 0x1c /* D channel extended interrupt */
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#define D_EXIM 0x20 /* D channel extended interrupt mask */
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#define D_STAR 0x24 /* D channel status register */
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#define D_RSTA 0x28 /* D channel receive status */
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#define D_SAM 0x2c /* D channel address mask 1 */
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#define D_SAP1 0x30 /* D channel individual SAPI 1 */
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#define D_SAP2 0x34 /* D channel individual SAPI 2 */
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#define D_TAM 0x38 /* D channel address mask 2 */
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#define D_TEI1 0x3c /* D channel individual TEI 1 */
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#define D_TEI2 0x40 /* D channel individual TEI 2 */
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#define D_RBCH 0x44 /* D channel receive frame byte count high */
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#define D_RBCL 0x48 /* D channel receive frame byte count low */
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#define D_CTL 0x54 /* D channel control register */
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/*---------------------------------------------------------------------------*
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* B-channel base offsets
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*---------------------------------------------------------------------------*/
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#define B1_CHAN_OFFSET 0x80 /* B1 channel offset */
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#define B2_CHAN_OFFSET 0xc0 /* B2 channel offset */
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/*---------------------------------------------------------------------------*
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* B-channel register offsets, from base
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*---------------------------------------------------------------------------*/
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#define B_RFIFO 0x00 /* B channel receive FIFO */
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#define B_XFIFO 0x04 /* B channel transmit FIFO */
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#define B_CMDR 0x08 /* B channel command register */
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#define B_MODE 0x0c /* B channel mode control */
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#define B_EXIR 0x10 /* B channel extended interrupt */
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#define B_EXIM 0x14 /* B channel extended interrupt mask */
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#define B_STAR 0x18 /* B channel status register */
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#define B_ADM1 0x1c /* B channel address mask 1 */
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#define B_ADM2 0x20 /* B channel address mask 2 */
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#define B_ADR1 0x24 /* B channel address 1 */
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#define B_ADR2 0x28 /* B channel address 2 */
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#define B_RBCL 0x2c /* B channel receive frame byte count high */
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#define B_RBCH 0x30 /* B channel receive frame byte count low */
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/*---------------------------------------------------------------------------*
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* Remaining control register offsets.
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*---------------------------------------------------------------------------*/
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#define ISTA 0x14 /* Interrupt status register */
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#define IMASK 0x18 /* Interrupt mask register */
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#define TIMR2 0x4c /* Timer 2 */
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#define L1_RC 0x50 /* GCI layer 1 ready code */
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#define CIR 0x58 /* Command/Indication receive */
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#define CIX 0x5c /* Command/Indication transmit */
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#define SQR 0x60 /* S/Q channel receive register */
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#define SQX 0x64 /* S/Q channel transmit register */
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#define PCTL 0x68 /* Peripheral control register */
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#define MOR 0x6c /* Monitor receive channel */
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#define MOX 0x70 /* Monitor transmit channel */
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#define MOSR 0x74 /* Monitor channel status register */
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#define MOCR 0x78 /* Monitor channel control register */
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#define GCR 0x7c /* GCI mode control register */
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#define XADDR 0xf4 /* Peripheral address register */
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#define XDATA 0xf8 /* Peripheral data register */
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#define EPCTL 0xfc /* Serial EEPROM control */
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/*---------------------------------------------------------------------------*
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* register bits
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*---------------------------------------------------------------------------*/
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#define D_CMDR_RACK 0x80
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#define D_CMDR_RRST 0x40
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#define D_CMDR_STT 0x10
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#define D_CMDR_XMS 0x08
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#define D_CMDR_XME 0x02
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#define D_CMDR_XRST 0x01
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#define D_MODE_MMS 0x80
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#define D_MODE_RACT 0x40
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#define D_MODE_TMS 0x10
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#define D_MODE_TEE 0x08
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#define D_MODE_MFD 0x04
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#define D_MODE_DLP 0x02
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#define D_MODE_RLP 0x01
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#define D_TIMR_CNT(i) (((i) >> 5) & 0x07)
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#define D_TIMR_VAL(i) ((i) & 0x1f)
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#define ISTA_D_RMR 0x80
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#define ISTA_D_RME 0x40
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#define ISTA_D_XFR 0x20
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#define ISTA_XINT1 0x10
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#define ISTA_XINT0 0x08
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#define ISTA_D_EXI 0x04
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#define ISTA_B1_EXI 0x02
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#define ISTA_B2_EXI 0x01
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#define IMASK_D_RMR 0x80
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#define IMASK_D_RME 0x40
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#define IMASK_D_XFR 0x20
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#define IMASK_XINT1 0x10
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#define IMASK_XINT0 0x08
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#define IMASK_D_EXI 0x04
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#define IMASK_B1_EXI 0x02
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#define IMASK_B2_EXI 0x01
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#define D_EXIR_RDOV 0x80
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#define D_EXIR_XDUN 0x40
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#define D_EXIR_XCOL 0x20
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#define D_EXIR_TIN2 0x10
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#define D_EXIR_MOC 0x08
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#define D_EXIR_ISC 0x04
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#define D_EXIR_TEXP 0x02
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#define D_EXIR_WEXP 0x01
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#define D_EXIM_RDOV 0x80
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#define D_EXIM_XDUN 0x40
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#define D_EXIM_XCOL 0x20
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#define D_EXIM_TIM2 0x10
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#define D_EXIM_MOC 0x08
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#define D_EXIM_ISC 0x04
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#define D_EXIM_TEXP 0x02
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#define D_EXIM_WEXP 0x01
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#define D_STAR_XDOW 0x80
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#define D_STAR_XBZ 0x20
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#define D_STAR_DRDY 0x10
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#define D_RSTA_RDOV 0x40
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#define D_RSTA_CRCE 0x20
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#define D_RSTA_RMB 0x10
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#define D_RBCH_VN(i) (((i) >> 6) & 0x03)
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#define D_RBCH_LOV 0x20
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#define D_RBC(h,l) (((((h) & 0x1f)) << 8) + (l))
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#define D_TIMR2_TMD 0x80
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#define D_TIMR2_TBCN(i) ((i) & 0x3f)
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#define L1_RC_RC(i) ((i) & 0x0f)
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#define D_CTL_WTT(i) (((i) > 6) & 0x03)
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#define D_CTL_SRST 0x20
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#define D_CTL_TPS 0x04
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#define D_CTL_OPS(i) ((i) & 0x03)
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#define CIR_SCC 0x80
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#define CIR_ICC 0x40
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#define CIR_CODR(i) ((i) & 0x0f)
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#define CIX_ECK 0x00
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#define CIX_RST 0x01
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#define CIX_SCP 0x04
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#define CIX_SSP 0x02
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#define CIX_AR8 0x08
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#define CIX_AR10 0x09
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#define CIX_EAL 0x0a
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#define CIX_DRC 0x0f
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#define CIR_CE 0x07
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#define CIR_DRD 0x00
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#define CIR_LD 0x04
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#define CIR_ARD 0x08
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#define CIR_TI 0x0a
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#define CIR_ATI 0x0b
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#define CIR_AI8 0x0c
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#define CIR_AI10 0x0d
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#define CIR_CD 0x0f
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#define SQR_XIND1 0x80
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#define SQR_XIND0 0x40
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#define SQR_MSYN 0x20
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#define SQR_SCIE 0x10
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#define SQR_S(i) ((i) & 0x0f)
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#define SQX_SCIE 0x10
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#define SQX_Q(i) ((i) & 0x0f)
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#define B_CMDR_RACK 0x80
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#define B_CMDR_RRST 0x40
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#define B_CMDR_RACT 0x20
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#define B_CMDR_XMS 0x04
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#define B_CMDR_XME 0x02
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#define B_CMDR_XRST 0x01
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#define B_MODE_MMS 0x80
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#define B_MODE_ITF 0x40
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#define B_MODE_EPCM 0x20
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#define B_MODE_BSW1 0x10
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#define B_MODE_BSW0 0x08
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#define B_MODE_SW56 0x04
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#define B_MODE_FTS1 0x02
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#define B_MODE_FTS0 0x01
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#define B_EXIR_RMR 0x40
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#define B_EXIR_RME 0x20
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#define B_EXIR_RDOV 0x10
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#define B_EXIR_XFR 0x02
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#define B_EXIR_XDUN 0x01
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#define B_EXIM_RMR 0x40
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#define B_EXIM_RME 0x20
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#define B_EXIM_RDOV 0x10
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#define B_EXIM_XFR 0x02
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#define B_EXIM_XDUN 0x01
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#define B_STAR_RDOV 0x40
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#define B_STAR_CRCE 0x20
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#define B_STAR_RMB 0x10
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#define B_STAR_XDOW 0x04
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#define B_STAR_XBZ 0x01
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#define B_RBC(h,l) (((((h) & 0x1f)) << 8) + (l))
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#endif /* _I4B_W6692_H_ */
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