freebsd-skq/sys/mips
adrian 05283b18cc arge: use 1-byte TX and RX alignment for AR9330/AR9331.
This part seems to work bug-free with single byte TX/RX buffer alignment.

This drops the CPU requirement to bridge 100mbit iperf from 100% CPU
to ~ 50% CPU.

Tested:

* AP121 (AR9330) SoC, highly magic netbooted kernel + USB rootfs
  due to 4mb flash, 16mb RAM; doing bridging between arge0 and arge1.

Notes:

* Yes, I likely can also turn this on for the AR934x SoC family now.

  But since hardware design apparently follows similar branching
  strategies to software design, I'll go and make sure all the AR934x's
  that made it out into shipping products work before I flip it on.
2015-10-22 08:02:27 +00:00
..
adm5120 Add domain support to PCI bus allocation 2015-09-16 23:34:51 +00:00
alchemy Fix a typo introduced in r257338. 2013-10-31 02:27:16 +00:00
atheros arge: use 1-byte TX and RX alignment for AR9330/AR9331. 2015-10-22 08:02:27 +00:00
beri preload_search_info: make sure mod is set 2015-08-21 15:57:57 +00:00
cavium Add domain support to PCI bus allocation 2015-09-16 23:34:51 +00:00
conf Disable SWAPPING as we don't do it on this board. 2015-10-20 19:32:26 +00:00
gxemul Add 32-bit support for Gxemul's oldtestmips machine emulation 2013-09-04 20:34:36 +00:00
idt Add domain support to PCI bus allocation 2015-09-16 23:34:51 +00:00
include Switch from a stub to a real implementation of pmap_page_set_attr() for mips, 2015-10-21 14:57:59 +00:00
malta Add domain support to PCI bus allocation 2015-09-16 23:34:51 +00:00
mips Treat mbufs as cacheline-aligned. Even when the transfer begins at an 2015-10-21 19:24:20 +00:00
nlm Add domain support to PCI bus allocation 2015-09-16 23:34:51 +00:00
rmi Add domain support to PCI bus allocation 2015-09-16 23:34:51 +00:00
rt305x Add support for the uart classes to set their default register shift value. 2015-04-11 17:16:23 +00:00
sentry5 Merge from vmobj-rwlock branch: 2013-02-26 01:00:11 +00:00
sibyte Devices that rely on hints or identify routines for discovery need to 2013-10-29 14:07:31 +00:00