f51629e24e
263030, 263033, 263034, 263056, 263057, Remove all the redundant external declarations of exception vectors and runtime setting of the pointers that's scattered around various places. Remove all traces of support for ARM chips prior to the arm9 series. Make the default exception handler vectors point to where I thought they were already pointing: the default handlers (not a panic that says there is no default handler). Eliminate irq_dispatch.S. Move the data items it contained into arm/intr.c and the functionality it provided into arm/exception.S. Move the exception vector table (so-called "page0" data) into exception.S and eliminate vectors.S. Change the way the asm GET_CURTHREAD_PTR() macro is defined so that code using it doesn't have to have an "AST_LOCALS" macro somewhere in the file. Arrange for arm fork_trampoline() to return to userland via the standard swi_exit code in exception.S instead of having its own inline expansion of the DO_AST and PULLFRAME macros. Now that the PUSHFRAME and PULLFRAME macros are used only in the swi entry/exit code, they don't need to be macros. Except that didn't work and the whole change was reverted. Remove some unnecessary indirection and jump right to the handler functions. Use panic rather than printf to "handle" an arm26 address exception (should never happen on arm32). Remove the unreferenced DATA() macro. Remove #include <machine/asmacros.h> from files that don't need it.
102 lines
3.5 KiB
C
102 lines
3.5 KiB
C
/* $NetBSD: sysarch.h,v 1.5 2003/09/11 09:40:12 kleink Exp $ */
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/*-
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* Copyright (c) 1996-1997 Mark Brinicombe.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef _ARM_SYSARCH_H_
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#define _ARM_SYSARCH_H_
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#include <machine/armreg.h>
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/*
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* The ARM_TP_ADDRESS points to a special purpose page, which is used as local
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* store for the ARM per-thread data and Restartable Atomic Sequences support.
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* Put it just above the "high" vectors' page.
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* The cpu_switch() code assumes ARM_RAS_START is ARM_TP_ADDRESS + 4, and
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* ARM_RAS_END is ARM_TP_ADDRESS + 8, so if that ever changes, be sure to
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* update the cpu_switch() (and cpu_throw()) code as well.
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* In addition, code in arm/include/atomic.h and arm/arm/exception.S
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* assumes that ARM_RAS_END is at ARM_RAS_START+4, so be sure to update those
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* if ARM_RAS_END moves in relation to ARM_RAS_START (look for occurrences
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* of ldr/str rm,[rn, #4]).
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*/
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/* ARM_TP_ADDRESS is needed for processors that don't support
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* the exclusive-access opcodes introduced with ARMv6K. */
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/* TODO: #if !defined(_HAVE_ARMv6K_INSTRUCTIONS) */
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#if !defined (__ARM_ARCH_7__) && \
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!defined (__ARM_ARCH_7A__) && \
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!defined (__ARM_ARCH_6K__) && \
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!defined (__ARM_ARCH_6ZK__)
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#define ARM_TP_ADDRESS (ARM_VECTORS_HIGH + 0x1000)
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#define ARM_RAS_START (ARM_TP_ADDRESS + 4)
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#define ARM_RAS_END (ARM_TP_ADDRESS + 8)
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#endif
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#ifndef LOCORE
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#ifndef __ASSEMBLER__
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#include <sys/cdefs.h>
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/*
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* Pickup definition of uintptr_t
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*/
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#include <sys/stdint.h>
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/*
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* Architecture specific syscalls (arm)
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*/
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#define ARM_SYNC_ICACHE 0
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#define ARM_DRAIN_WRITEBUF 1
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#define ARM_SET_TP 2
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#define ARM_GET_TP 3
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struct arm_sync_icache_args {
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uintptr_t addr; /* Virtual start address */
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size_t len; /* Region size */
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};
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#ifndef _KERNEL
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__BEGIN_DECLS
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int arm_sync_icache (u_int addr, int len);
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int arm_drain_writebuf (void);
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int sysarch(int, void *);
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__END_DECLS
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#endif
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#endif /* __ASSEMBLER__ */
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#endif /* LOCORE */
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#endif /* !_ARM_SYSARCH_H_ */
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