064bee341e
This is just prior to the bhyve_npt_pmap import so will allow just the change to be merged for easier debug.
282 lines
6.4 KiB
C
282 lines
6.4 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/smp.h>
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#include <machine/specialreg.h>
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#include <machine/vmm.h>
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#include "vmm_lapic.h"
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#include "vmm_msr.h"
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#define VMM_MSR_F_EMULATE 0x01
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#define VMM_MSR_F_READONLY 0x02
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#define VMM_MSR_F_INVALID 0x04 /* guest_msr_valid() can override this */
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struct vmm_msr {
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int num;
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int flags;
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uint64_t hostval;
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};
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static struct vmm_msr vmm_msr[] = {
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{ MSR_LSTAR, 0 },
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{ MSR_CSTAR, 0 },
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{ MSR_STAR, 0 },
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{ MSR_SF_MASK, 0 },
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{ MSR_PAT, VMM_MSR_F_EMULATE | VMM_MSR_F_INVALID },
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{ MSR_BIOS_SIGN,VMM_MSR_F_EMULATE },
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{ MSR_MCG_CAP, VMM_MSR_F_EMULATE | VMM_MSR_F_READONLY },
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#if 0 /* XXX unsupported on AMD */
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{ MSR_IA32_PLATFORM_ID, VMM_MSR_F_EMULATE | VMM_MSR_F_READONLY },
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{ MSR_IA32_MISC_ENABLE, VMM_MSR_F_EMULATE | VMM_MSR_F_READONLY },
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#endif
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};
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#define vmm_msr_num (sizeof(vmm_msr) / sizeof(vmm_msr[0]))
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CTASSERT(VMM_MSR_NUM >= vmm_msr_num);
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#define readonly_msr(idx) \
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((vmm_msr[(idx)].flags & VMM_MSR_F_READONLY) != 0)
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#define emulated_msr(idx) \
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((vmm_msr[(idx)].flags & VMM_MSR_F_EMULATE) != 0)
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#define invalid_msr(idx) \
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((vmm_msr[(idx)].flags & VMM_MSR_F_INVALID) != 0)
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void
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vmm_msr_init(void)
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{
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int i;
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for (i = 0; i < vmm_msr_num; i++) {
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if (emulated_msr(i))
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continue;
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/*
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* XXX this assumes that the value of the host msr does not
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* change after we have cached it.
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*/
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vmm_msr[i].hostval = rdmsr(vmm_msr[i].num);
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}
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}
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void
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guest_msrs_init(struct vm *vm, int cpu)
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{
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int i;
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#if 0
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uint64_t *guest_msrs, misc;
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#else
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uint64_t *guest_msrs;
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#endif
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guest_msrs = vm_guest_msrs(vm, cpu);
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for (i = 0; i < vmm_msr_num; i++) {
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switch (vmm_msr[i].num) {
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case MSR_LSTAR:
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case MSR_CSTAR:
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case MSR_STAR:
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case MSR_SF_MASK:
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case MSR_BIOS_SIGN:
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case MSR_MCG_CAP:
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guest_msrs[i] = 0;
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break;
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case MSR_PAT:
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guest_msrs[i] = PAT_VALUE(0, PAT_WRITE_BACK) |
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PAT_VALUE(1, PAT_WRITE_THROUGH) |
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PAT_VALUE(2, PAT_UNCACHED) |
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PAT_VALUE(3, PAT_UNCACHEABLE) |
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PAT_VALUE(4, PAT_WRITE_BACK) |
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PAT_VALUE(5, PAT_WRITE_THROUGH) |
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PAT_VALUE(6, PAT_UNCACHED) |
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PAT_VALUE(7, PAT_UNCACHEABLE);
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break;
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#if 0 /* XXX unsupported on AMD */
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case MSR_IA32_MISC_ENABLE:
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misc = rdmsr(MSR_IA32_MISC_ENABLE);
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/*
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* Set mandatory bits
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* 11: branch trace disabled
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* 12: PEBS unavailable
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* Clear unsupported features
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* 16: SpeedStep enable
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* 18: enable MONITOR FSM
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*/
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misc |= (1 << 12) | (1 << 11);
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misc &= ~((1 << 18) | (1 << 16));
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guest_msrs[i] = misc;
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break;
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case MSR_IA32_PLATFORM_ID:
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guest_msrs[i] = 0;
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break;
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#endif
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default:
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panic("guest_msrs_init: missing initialization for msr "
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"0x%0x", vmm_msr[i].num);
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}
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}
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}
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static int
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msr_num_to_idx(u_int num)
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{
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int i;
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for (i = 0; i < vmm_msr_num; i++)
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if (vmm_msr[i].num == num)
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return (i);
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return (-1);
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}
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int
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emulate_wrmsr(struct vm *vm, int cpu, u_int num, uint64_t val)
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{
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int idx;
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uint64_t *guest_msrs;
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if (lapic_msr(num))
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return (lapic_wrmsr(vm, cpu, num, val));
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idx = msr_num_to_idx(num);
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if (idx < 0 || invalid_msr(idx))
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return (EINVAL);
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if (!readonly_msr(idx)) {
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guest_msrs = vm_guest_msrs(vm, cpu);
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/* Stash the value */
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guest_msrs[idx] = val;
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/* Update processor state for non-emulated MSRs */
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if (!emulated_msr(idx))
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wrmsr(vmm_msr[idx].num, val);
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}
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return (0);
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}
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int
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emulate_rdmsr(struct vm *vm, int cpu, u_int num)
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{
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int error, idx;
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uint32_t eax, edx;
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uint64_t result, *guest_msrs;
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if (lapic_msr(num)) {
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error = lapic_rdmsr(vm, cpu, num, &result);
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goto done;
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}
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idx = msr_num_to_idx(num);
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if (idx < 0 || invalid_msr(idx)) {
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error = EINVAL;
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goto done;
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}
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guest_msrs = vm_guest_msrs(vm, cpu);
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result = guest_msrs[idx];
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/*
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* If this is not an emulated msr register make sure that the processor
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* state matches our cached state.
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*/
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if (!emulated_msr(idx) && (rdmsr(num) != result)) {
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panic("emulate_rdmsr: msr 0x%0x has inconsistent cached "
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"(0x%016lx) and actual (0x%016lx) values", num,
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result, rdmsr(num));
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}
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error = 0;
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done:
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if (error == 0) {
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eax = result;
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edx = result >> 32;
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error = vm_set_register(vm, cpu, VM_REG_GUEST_RAX, eax);
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if (error)
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panic("vm_set_register(rax) error %d", error);
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error = vm_set_register(vm, cpu, VM_REG_GUEST_RDX, edx);
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if (error)
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panic("vm_set_register(rdx) error %d", error);
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}
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return (error);
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}
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void
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restore_guest_msrs(struct vm *vm, int cpu)
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{
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int i;
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uint64_t *guest_msrs;
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guest_msrs = vm_guest_msrs(vm, cpu);
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for (i = 0; i < vmm_msr_num; i++) {
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if (emulated_msr(i))
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continue;
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else
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wrmsr(vmm_msr[i].num, guest_msrs[i]);
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}
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}
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void
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restore_host_msrs(struct vm *vm, int cpu)
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{
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int i;
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for (i = 0; i < vmm_msr_num; i++) {
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if (emulated_msr(i))
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continue;
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else
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wrmsr(vmm_msr[i].num, vmm_msr[i].hostval);
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}
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}
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/*
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* Must be called by the CPU-specific code before any guests are
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* created
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*/
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void
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guest_msr_valid(int msr)
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{
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int i;
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for (i = 0; i < vmm_msr_num; i++) {
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if (vmm_msr[i].num == msr && invalid_msr(i)) {
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vmm_msr[i].flags &= ~VMM_MSR_F_INVALID;
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}
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}
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}
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