517 lines
14 KiB
C
517 lines
14 KiB
C
/*-
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* Principal Author: Parag Patel
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* Copyright (c) 2001
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Additonal Copyright (c) 2001 by Traakan Software under same licence.
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* Secondary Author: Matthew Jacob
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
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*/
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/*
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* Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and
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* 1000baseSX PHY.
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* Nathan Binkert <nate@openbsd.org>
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* Jung-uk Kim <jkim@niksun.com>
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/bus.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include "miidevs.h"
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#include <dev/mii/e1000phyreg.h>
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#include "miibus_if.h"
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static int e1000phy_probe(device_t);
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static int e1000phy_attach(device_t);
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struct e1000phy_softc {
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struct mii_softc mii_sc;
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int mii_model;
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};
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static device_method_t e1000phy_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, e1000phy_probe),
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DEVMETHOD(device_attach, e1000phy_attach),
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DEVMETHOD(device_detach, mii_phy_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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{ 0, 0 }
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};
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static devclass_t e1000phy_devclass;
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static driver_t e1000phy_driver = {
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"e1000phy",
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e1000phy_methods,
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sizeof(struct e1000phy_softc)
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};
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DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0);
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static int e1000phy_service(struct mii_softc *, struct mii_data *, int);
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static void e1000phy_status(struct mii_softc *);
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static void e1000phy_reset(struct mii_softc *);
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static int e1000phy_mii_phy_auto(struct e1000phy_softc *, int);
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static const struct mii_phydesc e1000phys[] = {
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MII_PHY_DESC(MARVELL, E1000),
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MII_PHY_DESC(MARVELL, E1011),
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MII_PHY_DESC(MARVELL, E1000_3),
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MII_PHY_DESC(MARVELL, E1000S),
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MII_PHY_DESC(MARVELL, E1000_5),
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MII_PHY_DESC(MARVELL, E1101),
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MII_PHY_DESC(MARVELL, E3082),
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MII_PHY_DESC(MARVELL, E1112),
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MII_PHY_DESC(MARVELL, E1149),
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MII_PHY_DESC(MARVELL, E1111),
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MII_PHY_DESC(MARVELL, E1116),
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MII_PHY_DESC(MARVELL, E1116R),
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MII_PHY_DESC(MARVELL, E1118),
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MII_PHY_DESC(MARVELL, E3016),
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MII_PHY_DESC(MARVELL, PHYG65G),
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MII_PHY_DESC(xxMARVELL, E1000),
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MII_PHY_DESC(xxMARVELL, E1011),
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MII_PHY_DESC(xxMARVELL, E1000_3),
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MII_PHY_DESC(xxMARVELL, E1000_5),
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MII_PHY_DESC(xxMARVELL, E1111),
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MII_PHY_END
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};
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static int
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e1000phy_probe(device_t dev)
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{
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return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT));
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}
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static int
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e1000phy_attach(device_t dev)
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{
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struct e1000phy_softc *esc;
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struct mii_softc *sc;
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struct mii_attach_args *ma;
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struct mii_data *mii;
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struct ifnet *ifp;
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esc = device_get_softc(dev);
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sc = &esc->mii_sc;
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ma = device_get_ivars(dev);
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sc->mii_dev = device_get_parent(dev);
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mii = ma->mii_data;
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LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
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sc->mii_flags = miibus_get_flags(dev);
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sc->mii_inst = mii->mii_instance++;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_service = e1000phy_service;
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sc->mii_pdata = mii;
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sc->mii_flags |= MIIF_NOMANPAUSE;
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esc->mii_model = MII_MODEL(ma->mii_id2);
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ifp = sc->mii_pdata->mii_ifp;
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if (strcmp(ifp->if_dname, "msk") == 0 &&
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(sc->mii_flags & MIIF_MACPRIV0) != 0)
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sc->mii_flags |= MIIF_PHYPRIV0;
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switch (esc->mii_model) {
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case MII_MODEL_MARVELL_E1011:
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case MII_MODEL_MARVELL_E1112:
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if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK)
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sc->mii_flags |= MIIF_HAVEFIBER;
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break;
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case MII_MODEL_MARVELL_E1149:
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/*
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* Some 88E1149 PHY's page select is initialized to
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* point to other bank instead of copper/fiber bank
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* which in turn resulted in wrong registers were
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* accessed during PHY operation. It is believed that
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* page 0 should be used for copper PHY so reinitialize
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* E1000_EADR to select default copper PHY. If parent
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* device know the type of PHY(either copper or fiber),
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* that information should be used to select default
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* type of PHY.
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*/
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PHY_WRITE(sc, E1000_EADR, 0);
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break;
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}
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e1000phy_reset(sc);
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sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
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if (sc->mii_capabilities & BMSR_EXTSTAT)
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sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
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device_printf(dev, " ");
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mii_phy_add_media(sc);
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printf("\n");
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MIIBUS_MEDIAINIT(sc->mii_dev);
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return (0);
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}
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static void
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e1000phy_reset(struct mii_softc *sc)
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{
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struct e1000phy_softc *esc;
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uint16_t reg, page;
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esc = (struct e1000phy_softc *)sc;
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reg = PHY_READ(sc, E1000_SCR);
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if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) {
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reg &= ~E1000_SCR_AUTO_X_MODE;
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PHY_WRITE(sc, E1000_SCR, reg);
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if (esc->mii_model == MII_MODEL_MARVELL_E1112) {
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/* Select 1000BASE-X only mode. */
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page = PHY_READ(sc, E1000_EADR);
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PHY_WRITE(sc, E1000_EADR, 2);
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reg = PHY_READ(sc, E1000_SCR);
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reg &= ~E1000_SCR_MODE_MASK;
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reg |= E1000_SCR_MODE_1000BX;
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PHY_WRITE(sc, E1000_SCR, reg);
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if ((sc->mii_flags & MIIF_PHYPRIV0) != 0) {
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/* Set SIGDET polarity low for SFP module. */
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PHY_WRITE(sc, E1000_EADR, 1);
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reg = PHY_READ(sc, E1000_SCR);
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reg |= E1000_SCR_FIB_SIGDET_POLARITY;
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PHY_WRITE(sc, E1000_SCR, reg);
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}
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PHY_WRITE(sc, E1000_EADR, page);
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}
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} else {
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switch (esc->mii_model) {
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case MII_MODEL_MARVELL_E1111:
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case MII_MODEL_MARVELL_E1112:
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case MII_MODEL_MARVELL_E1116:
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case MII_MODEL_MARVELL_E1118:
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case MII_MODEL_MARVELL_E1149:
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case MII_MODEL_MARVELL_PHYG65G:
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/* Disable energy detect mode. */
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reg &= ~E1000_SCR_EN_DETECT_MASK;
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reg |= E1000_SCR_AUTO_X_MODE;
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if (esc->mii_model == MII_MODEL_MARVELL_E1116)
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reg &= ~E1000_SCR_POWER_DOWN;
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reg |= E1000_SCR_ASSERT_CRS_ON_TX;
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break;
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case MII_MODEL_MARVELL_E3082:
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reg |= (E1000_SCR_AUTO_X_MODE >> 1);
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reg |= E1000_SCR_ASSERT_CRS_ON_TX;
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break;
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case MII_MODEL_MARVELL_E3016:
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reg |= E1000_SCR_AUTO_MDIX;
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reg &= ~(E1000_SCR_EN_DETECT |
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E1000_SCR_SCRAMBLER_DISABLE);
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reg |= E1000_SCR_LPNP;
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/* XXX Enable class A driver for Yukon FE+ A0. */
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PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001);
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break;
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default:
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reg &= ~E1000_SCR_AUTO_X_MODE;
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reg |= E1000_SCR_ASSERT_CRS_ON_TX;
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break;
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}
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if (esc->mii_model != MII_MODEL_MARVELL_E3016) {
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/* Auto correction for reversed cable polarity. */
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reg &= ~E1000_SCR_POLARITY_REVERSAL;
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}
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PHY_WRITE(sc, E1000_SCR, reg);
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if (esc->mii_model == MII_MODEL_MARVELL_E1116 ||
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esc->mii_model == MII_MODEL_MARVELL_E1149) {
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PHY_WRITE(sc, E1000_EADR, 2);
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reg = PHY_READ(sc, E1000_SCR);
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reg |= E1000_SCR_RGMII_POWER_UP;
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PHY_WRITE(sc, E1000_SCR, reg);
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PHY_WRITE(sc, E1000_EADR, 0);
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}
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}
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switch (esc->mii_model) {
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case MII_MODEL_MARVELL_E3082:
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case MII_MODEL_MARVELL_E1112:
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case MII_MODEL_MARVELL_E1118:
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break;
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case MII_MODEL_MARVELL_E1116:
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page = PHY_READ(sc, E1000_EADR);
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/* Select page 3, LED control register. */
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PHY_WRITE(sc, E1000_EADR, 3);
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PHY_WRITE(sc, E1000_SCR,
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E1000_SCR_LED_LOS(1) | /* Link/Act */
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E1000_SCR_LED_INIT(8) | /* 10Mbps */
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E1000_SCR_LED_STAT1(7) | /* 100Mbps */
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E1000_SCR_LED_STAT0(7)); /* 1000Mbps */
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/* Set blink rate. */
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PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) |
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E1000_BLINK_RATE(E1000_BLINK_84MS));
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PHY_WRITE(sc, E1000_EADR, page);
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break;
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case MII_MODEL_MARVELL_E3016:
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/* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */
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PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04);
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/* Integrated register calibration workaround. */
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PHY_WRITE(sc, 0x1D, 17);
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PHY_WRITE(sc, 0x1E, 0x3F60);
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break;
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default:
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/* Force TX_CLK to 25MHz clock. */
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reg = PHY_READ(sc, E1000_ESCR);
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reg |= E1000_ESCR_TX_CLK_25;
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PHY_WRITE(sc, E1000_ESCR, reg);
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break;
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}
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/* Reset the PHY so all changes take effect. */
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reg = PHY_READ(sc, E1000_CR);
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reg |= E1000_CR_RESET;
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PHY_WRITE(sc, E1000_CR, reg);
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}
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static int
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e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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struct e1000phy_softc *esc = (struct e1000phy_softc *)sc;
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uint16_t speed, gig;
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int reg;
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switch (cmd) {
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case MII_POLLSTAT:
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break;
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case MII_MEDIACHG:
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/*
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* If the interface is not up, don't do anything.
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
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e1000phy_mii_phy_auto(esc, ife->ifm_media);
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break;
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}
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speed = 0;
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_1000_T:
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if ((sc->mii_extcapabilities &
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(EXTSR_1000TFDX | EXTSR_1000THDX)) == 0)
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return (EINVAL);
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speed = E1000_CR_SPEED_1000;
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break;
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case IFM_1000_SX:
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if ((sc->mii_extcapabilities &
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(EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0)
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return (EINVAL);
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speed = E1000_CR_SPEED_1000;
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break;
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case IFM_100_TX:
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speed = E1000_CR_SPEED_100;
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break;
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case IFM_10_T:
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speed = E1000_CR_SPEED_10;
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break;
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case IFM_NONE:
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reg = PHY_READ(sc, E1000_CR);
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PHY_WRITE(sc, E1000_CR,
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reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN);
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goto done;
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default:
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return (EINVAL);
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}
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if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
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speed |= E1000_CR_FULL_DUPLEX;
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gig = E1000_1GCR_1000T_FD;
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} else
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gig = E1000_1GCR_1000T;
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reg = PHY_READ(sc, E1000_CR);
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reg &= ~E1000_CR_AUTO_NEG_ENABLE;
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PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);
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if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
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gig |= E1000_1GCR_MS_ENABLE;
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if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
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gig |= E1000_1GCR_MS_VALUE;
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PHY_WRITE(sc, E1000_1GCR, gig);
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} else if ((sc->mii_extcapabilities &
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(EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
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PHY_WRITE(sc, E1000_1GCR, 0);
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PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD);
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PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET);
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done:
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break;
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case MII_TICK:
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/*
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* Is the interface even up?
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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return (0);
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/*
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* Only used for autonegotiation.
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*/
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
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sc->mii_ticks = 0;
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break;
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}
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/*
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* check for link.
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* Read the status register twice; BMSR_LINK is latch-low.
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*/
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reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
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if (reg & BMSR_LINK) {
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sc->mii_ticks = 0;
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break;
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}
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/* Announce link loss right after it happens. */
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if (sc->mii_ticks++ == 0)
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break;
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if (sc->mii_ticks <= sc->mii_anegticks)
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break;
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sc->mii_ticks = 0;
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e1000phy_reset(sc);
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e1000phy_mii_phy_auto(esc, ife->ifm_media);
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break;
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}
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/* Update the media status. */
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e1000phy_status(sc);
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/* Callback if something changed. */
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mii_phy_update(sc, cmd);
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return (0);
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}
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static void
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e1000phy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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int bmcr, bmsr, ssr;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
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bmcr = PHY_READ(sc, E1000_CR);
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ssr = PHY_READ(sc, E1000_SSR);
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if (bmsr & E1000_SR_LINK_STATUS)
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mii->mii_media_status |= IFM_ACTIVE;
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if (bmcr & E1000_CR_LOOPBACK)
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mii->mii_media_active |= IFM_LOOP;
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if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 &&
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(ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
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switch (ssr & E1000_SSR_SPEED) {
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|
case E1000_SSR_1000MBS:
|
|
mii->mii_media_active |= IFM_1000_T;
|
|
break;
|
|
case E1000_SSR_100MBS:
|
|
mii->mii_media_active |= IFM_100_TX;
|
|
break;
|
|
case E1000_SSR_10MBS:
|
|
mii->mii_media_active |= IFM_10_T;
|
|
break;
|
|
default:
|
|
mii->mii_media_active |= IFM_NONE;
|
|
return;
|
|
}
|
|
} else {
|
|
/*
|
|
* Some fiber PHY(88E1112) does not seem to set resolved
|
|
* speed so always assume we've got IFM_1000_SX.
|
|
*/
|
|
mii->mii_media_active |= IFM_1000_SX;
|
|
}
|
|
|
|
if (ssr & E1000_SSR_DUPLEX) {
|
|
mii->mii_media_active |= IFM_FDX;
|
|
if ((sc->mii_flags & MIIF_HAVEFIBER) == 0)
|
|
mii->mii_media_active |= mii_phy_flowstatus(sc);
|
|
} else
|
|
mii->mii_media_active |= IFM_HDX;
|
|
|
|
if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
|
|
if (((PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR)) &
|
|
E1000_1GSR_MS_CONFIG_RES) != 0)
|
|
mii->mii_media_active |= IFM_ETH_MASTER;
|
|
}
|
|
}
|
|
|
|
static int
|
|
e1000phy_mii_phy_auto(struct e1000phy_softc *esc, int media)
|
|
{
|
|
struct mii_softc *sc;
|
|
uint16_t reg;
|
|
|
|
sc = &esc->mii_sc;
|
|
if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
|
|
reg = PHY_READ(sc, E1000_AR);
|
|
reg &= ~(E1000_AR_PAUSE | E1000_AR_ASM_DIR);
|
|
reg |= E1000_AR_10T | E1000_AR_10T_FD |
|
|
E1000_AR_100TX | E1000_AR_100TX_FD;
|
|
if ((media & IFM_FLOW) != 0 ||
|
|
(sc->mii_flags & MIIF_FORCEPAUSE) != 0)
|
|
reg |= E1000_AR_PAUSE | E1000_AR_ASM_DIR;
|
|
PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD);
|
|
} else
|
|
PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X);
|
|
if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
|
|
PHY_WRITE(sc, E1000_1GCR,
|
|
E1000_1GCR_1000T_FD | E1000_1GCR_1000T);
|
|
PHY_WRITE(sc, E1000_CR,
|
|
E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG);
|
|
|
|
return (EJUSTRETURN);
|
|
}
|