Hans Petter Selasky 08aa4c94b8 Try to fix DWC OTG regression issues with full and low speed devices:
- Remove double buffering interrupt and isochronous traffic via the
transaction translator. It can be avoided because the DWC OTG will
always delay the start split transactions for interrupt and
isochronous traffic, but will not delay the complete split
transactions, if we set the odd frame bit correctly.
- Need to check the transfer cache field in the device done function
to be sure all allocated channels are freed and not the transfer first
one. This seems to resolve the control endpoint transfer type quirk
which is now removed.
- Make sure any received data upon TX is dumped else RX path will
stop.
- Transmit isochronous data before receiving isochronous data as a
means to optimise the TT schedule.
- Implement a simple TT bandwidth scheduler.
- Cleanup use of old "td->error" variable.
- On interrupt IN traffic via the transaction translator we simply
ignore missed transfer opportunities and silently retry the
transaction upon next available time slot.

MFC after:	3 days
2014-06-05 18:17:40 +00:00
..
2014-04-07 20:44:00 +00:00
2014-04-17 12:22:08 +00:00
2014-02-06 13:28:06 +00:00
2014-04-30 20:52:38 +00:00
2014-04-05 22:43:18 +00:00