af3dc4a7ca
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
153 lines
6.5 KiB
C
153 lines
6.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91_SSCREG_H
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#define ARM_AT91_AT91_SSCREG_H
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/* Registers */
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#define SSC_CR 0x00 /* Control Register */
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#define SSC_CMR 0x04 /* Clock Mode Register */
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/* 0x08 Reserved */
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/* 0x0c Reserved */
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#define SSC_RCMR 0x10 /* Receive Clock Mode Register */
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#define SSC_RFMR 0x14 /* Receive Frame Mode Register */
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#define SSC_TCMR 0x18 /* Transmit Clock Mode Register */
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#define SSC_TFMR 0x1c /* Transmit Frame Mode register */
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#define SSC_RHR 0x20 /* Receive Holding Register */
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#define SSC_THR 0x24 /* Transmit Holding Register */
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/* 0x28 Reserved */
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/* 0x2c Reserved */
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#define SSC_RSHR 0x30 /* Receive Sync Holding Register */
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#define SSC_TSHR 0x34 /* Transmit Sync Holding Register */
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/* 0x38 Reserved */
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/* 0x3c Reserved */
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#define SSC_SR 0x40 /* Status Register */
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#define SSC_IER 0x44 /* Interrupt Enable Register */
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#define SSC_IDR 0x48 /* Interrupt Disable Register */
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#define SSC_IMR 0x4c /* Interrupt Mask Register */
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/* And PDC registers */
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/* SSC_CR */
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#define SSC_CR_RXEN (1u << 0) /* RXEN: Receive Enable */
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#define SSC_CR_RXDIS (1u << 1) /* RXDIS: Receive Disable */
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#define SSC_CR_TXEN (1u << 8) /* TXEN: Transmit Enable */
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#define SSC_CR_TXDIS (1u << 9) /* TXDIS: Transmit Disable */
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#define SSC_CR_SWRST (1u << 15) /* SWRST: Software Reset */
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/* SSC_CMR */
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#define SSC_CMR_DIV 0xfffu /* DIV: Clock Divider mask */
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/* SSC_RCMR */
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#define SSC_RCMR_PERIOD (0xffu << 24) /* PERIOD: Receive Period Divider sel*/
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#define SSC_RCMR_STTDLY (0xffu << 16) /* STTDLY: Receive Start Delay */
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#define SSC_RCMR_START (0xfu << 8) /* START: Receive Start Sel */
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#define SSC_RCMR_START_CONT (0u << 8)
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#define SSC_RCMR_START_TX_START (1u << 8)
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#define SSC_RCMR_START_LOW_RF (2u << 8)
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#define SSC_RCMR_START_HIGH_RF (3u << 8)
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#define SSC_RCMR_START_FALL_EDGE_RF (4u << 8)
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#define SSC_RCMR_START_RISE_EDGE_RF (5u << 8)
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#define SSC_RCMR_START_LEVEL_CHANGE_RF (6u << 8)
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#define SSC_RCMR_START_ANY_EDGE_RF (7u << 8)
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#define SSC_RCMR_CKI (1u << 5) /* CKI: Receive Clock Inversion */
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#define SSC_RCMR_CKO (7u << 2) /* CKO: Receive Clock Output Mode Sel*/
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#define SSC_RCMR_CKO_NONE (0u << 2)
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#define SSC_RCMR_CKO_CONTINUOUS (1u << 2)
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#define SSC_RCMR_CKS (3u) /* CKS: Receive Clock Selection */
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#define SSC_RCMR_CKS_DIVIDED (0)
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#define SSC_RCMR_CKS_TK_CLOCK (1)
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#define SSC_RCMR_CKS_RK (2)
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/* SSC_RFMR */
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#define SSC_RFMR_FSEDGE (1u << 24) /* FSEDGE: Frame Sync Edge Detection */
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#define SSC_RFMR_FSOS (7u << 20) /* FSOS: Receive frame Sync Out sel */
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#define SSC_RFMR_FSOS_NONE (0u << 20)
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#define SSC_RFMR_FSOS_NEG_PULSE (1u << 20)
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#define SSC_RFMR_FSOS_POS_PULSE (2u << 20)
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#define SSC_RFMR_FSOS_LOW (3u << 20)
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#define SSC_RFMR_FSOS_HIGH (4u << 20)
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#define SSC_RFMR_FSOS_TOGGLE (5u << 20)
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#define SSC_RFMR_FSLEN (0xfu << 16) /* FSLEN: Receive Frame Sync Length */
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#define SSC_RFMR_DATNB (0xfu << 8) /* DATNB: Data Number per Frame */
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#define SSC_RFMR_MSFBF (1u << 7) /* MSBF: Most Significant Bit First */
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#define SSC_RFMR_LOOP (1u << 5) /* LOOP: Loop Mode */
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#define SSC_RFMR_DATLEN (0x1fu << 0) /* DATLEN: Data Length */
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/* SSC_TCMR */
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#define SSC_TCMR_PERIOD (0xffu << 24) /* PERIOD: Receive Period Divider sel*/
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#define SSC_TCMR_STTDLY (0xffu << 16) /* STTDLY: Receive Start Delay */
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#define SSC_TCMR_START (0xfu << 8) /* START: Receive Start Sel */
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#define SSC_TCMR_START_CONT (0u << 8)
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#define SSC_TCMR_START_RX_START (1u << 8)
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#define SSC_TCMR_START_LOW_RF (2u << 8)
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#define SSC_TCMR_START_HIGH_RF (3u << 8)
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#define SSC_TCMR_START_FALL_EDGE_RF (4u << 8)
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#define SSC_TCMR_START_RISE_EDGE_RF (5u << 8)
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#define SSC_TCMR_START_LEVEL_CHANGE_RF (6u << 8)
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#define SSC_TCMR_START_ANY_EDGE_RF (7u << 8)
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#define SSC_TCMR_CKI (1u << 5) /* CKI: Receive Clock Inversion */
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#define SSC_TCMR_CKO (7u << 2) /* CKO: Receive Clock Output Mode Sel*/
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#define SSC_TCMR_CKO_NONE (0u << 2)
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#define SSC_TCMR_CKO_CONTINUOUS (1u << 2)
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#define SSC_TCMR_CKS (3u) /* CKS: Receive Clock Selection */
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#define SSC_TCMR_CKS_DIVIDED (0)
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#define SSC_TCMR_CKS_RK_CLOCK (1)
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#define SSC_TCMR_CKS_TK (2)
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/* SSC_TFMR */
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#define SSC_TFMR_FSEDGE (1u << 24) /* FSEDGE: Frame Sync Edge Detection */
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#define SSC_TFMR_FSOS (7u << 20) /* FSOS: Receive frame Sync Out sel */
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#define SSC_TFMR_FSOS_NONE (0u << 20)
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#define SSC_TFMR_FSOS_NEG_PULSE (1u << 20)
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#define SSC_TFMR_FSOS_POS_PULSE (2u << 20)
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#define SSC_TFMR_FSOS_LOW (3u << 20)
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#define SSC_TFMR_FSOS_HIGH (4u << 20)
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#define SSC_TFMR_FSOS_TOGGLE (5u << 20)
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#define SSC_TFMR_FSLEN (0xfu << 16) /* FSLEN: Receive Frame Sync Length */
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#define SSC_TFMR_DATNB (0xfu << 8) /* DATNB: Data Number per Frame */
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#define SSC_TFMR_MSFBF (1u << 7) /* MSBF: Most Significant Bit First */
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#define SSC_TFMR_DATDEF (1u << 5) /* DATDEF: Data Default Value */
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#define SSC_TFMR_DATLEN (0x1fu << 0) /* DATLEN: Data Length */
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/* SSC_SR */
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#define SSC_SR_TXRDY (1u << 0)
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#define SSC_SR_TXEMPTY (1u << 1)
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#define SSC_SR_ENDTX (1u << 2)
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#define SSC_SR_TXBUFE (1u << 3)
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#define SSC_SR_RXRDY (1u << 4)
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#define SSC_SR_OVRUN (1u << 5)
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#define SSC_SR_ENDRX (1u << 6)
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#define SSC_SR_RXBUFF (1u << 7)
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#define SSC_SR_TXSYN (1u << 10)
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#define SSC_SR_RSSYN (1u << 11)
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#define SSC_SR_TXEN (1u << 16)
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#define SSC_SR_RXEN (1u << 17)
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#endif /* ARM_AT91_AT91_SSCREG_H */
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