Neel Natu 09eced2549 For level triggered interrupts clear the PIC IRR bit when the interrupt pin ...

is deasserted. Prior to this change each assertion on a level triggered irq
pin resulted in two interrupts being delivered to the CPU.

Differential Revision:	https://reviews.freebsd.org/D1310
Reviewed by:	tychon
MFC after:	1 week

2014-12-16 06:33:57 +00:00

..

acpica

don't set CR4 PSE bit on amd64

2014-07-23 15:53:29 +00:00

amd64

Improve support for XSAVE with debuggers.

2014-11-21 20:53:17 +00:00

conf

This configuration file removes several debugging options, including

2014-12-02 19:55:43 +00:00

ia32

Replace some calls to fuword() by fueword() with proper error checking.

2014-10-28 15:28:20 +00:00

include

Revert r274772: it is not valid on MIPS

2014-11-25 03:50:31 +00:00

linux32

Re-gen after r271743 implementing most of

2014-09-18 08:40:00 +00:00

pci

Pull in r267961 and r267973 again. Fix for issues reported will follow.

2014-06-28 03:56:17 +00:00

vmm

For level triggered interrupts clear the PIC IRR bit when the interrupt pin

2014-12-16 06:33:57 +00:00

Makefile

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