917 lines
28 KiB
C
917 lines
28 KiB
C
/*-
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* Copyright (c) 2009 Yahoo! Inc.
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* Copyright (c) 2011-2015 LSI Corp.
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* Copyright (c) 2013-2016 Avago Technologies
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD
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*
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* $FreeBSD$
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*/
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#ifndef _MPRVAR_H
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#define _MPRVAR_H
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#define MPR_DRIVER_VERSION "15.03.00.00-fbsd"
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#define MPR_DB_MAX_WAIT 2500
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#define MPR_REQ_FRAMES 2048
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#define MPR_PRI_REQ_FRAMES 128
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#define MPR_EVT_REPLY_FRAMES 32
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#define MPR_REPLY_FRAMES MPR_REQ_FRAMES
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#define MPR_CHAIN_FRAMES 2048
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#define MPR_MAXIO_PAGES (-1)
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#define MPR_SENSE_LEN SSD_FULL_SIZE
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#define MPR_MSI_MAX 1
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#define MPR_MSIX_MAX 96
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#define MPR_SGE64_SIZE 12
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#define MPR_SGE32_SIZE 8
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#define MPR_SGC_SIZE 8
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#define MPR_DEFAULT_CHAIN_SEG_SIZE 8
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#define MPR_MAX_CHAIN_ELEMENT_SIZE 16
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/*
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* PCIe NVMe Specific defines
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*/
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//SLM-for now just use the same value as a SAS disk
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#define NVME_QDEPTH MPR_REQ_FRAMES
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#define PRP_ENTRY_SIZE 8
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#define NVME_CMD_PRP1_OFFSET 24 /* PRP1 offset in NVMe cmd */
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#define NVME_CMD_PRP2_OFFSET 32 /* PRP2 offset in NVMe cmd */
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#define NVME_ERROR_RESPONSE_SIZE 16 /* Max NVME Error Response */
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#define HOST_PAGE_SIZE_4K 12
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#define MPR_FUNCTRACE(sc) \
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mpr_dprint((sc), MPR_TRACE, "%s\n", __func__)
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#define CAN_SLEEP 1
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#define NO_SLEEP 0
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#define MPR_PERIODIC_DELAY 1 /* 1 second heartbeat/watchdog check */
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#define MPR_ATA_ID_TIMEOUT 5 /* 5 second timeout for SATA ID cmd */
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#define MPR_MISSING_CHECK_DELAY 10 /* 10 seconds between missing check */
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#define IFAULT_IOP_OVER_TEMP_THRESHOLD_EXCEEDED 0x2810
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#define MPR_SCSI_RI_INVALID_FRAME (0x00000002)
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#define DEFAULT_SPINUP_WAIT 3 /* seconds to wait for spinup */
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#include <sys/endian.h>
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/*
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* host mapping related macro definitions
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*/
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#define MPR_MAPTABLE_BAD_IDX 0xFFFFFFFF
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#define MPR_DPM_BAD_IDX 0xFFFF
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#define MPR_ENCTABLE_BAD_IDX 0xFF
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#define MPR_MAX_MISSING_COUNT 0x0F
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#define MPR_DEV_RESERVED 0x20000000
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#define MPR_MAP_IN_USE 0x10000000
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#define MPR_MAP_BAD_ID 0xFFFFFFFF
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typedef uint8_t u8;
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typedef uint16_t u16;
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typedef uint32_t u32;
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typedef uint64_t u64;
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/**
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* struct dev_mapping_table - device mapping information
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* @physical_id: SAS address for drives or WWID for RAID volumes
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* @device_info: bitfield provides detailed info about the device
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* @phy_bits: bitfields indicating controller phys
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* @dpm_entry_num: index of this device in device persistent map table
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* @dev_handle: device handle for the device pointed by this entry
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* @id: target id
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* @missing_count: number of times the device not detected by driver
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* @hide_flag: Hide this physical disk/not (foreign configuration)
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* @init_complete: Whether the start of the day checks completed or not
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* @TLR_bits: Turn TLR support on or off
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*/
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struct dev_mapping_table {
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u64 physical_id;
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u32 device_info;
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u32 phy_bits;
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u16 dpm_entry_num;
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u16 dev_handle;
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u16 reserved1;
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u16 id;
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u8 missing_count;
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u8 init_complete;
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u8 TLR_bits;
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u8 reserved2;
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};
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/**
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* struct enc_mapping_table - mapping information about an enclosure
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* @enclosure_id: Logical ID of this enclosure
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* @start_index: index to the entry in dev_mapping_table
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* @phy_bits: bitfields indicating controller phys
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* @dpm_entry_num: index of this enclosure in device persistent map table
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* @enc_handle: device handle for the enclosure pointed by this entry
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* @num_slots: number of slots in the enclosure
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* @start_slot: Starting slot id
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* @missing_count: number of times the device not detected by driver
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* @removal_flag: used to mark the device for removal
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* @skip_search: used as a flag to include/exclude enclosure for search
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* @init_complete: Whether the start of the day checks completed or not
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*/
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struct enc_mapping_table {
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u64 enclosure_id;
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u32 start_index;
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u32 phy_bits;
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u16 dpm_entry_num;
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u16 enc_handle;
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u16 num_slots;
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u16 start_slot;
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u8 missing_count;
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u8 removal_flag;
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u8 skip_search;
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u8 init_complete;
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};
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/**
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* struct map_removal_table - entries to be removed from mapping table
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* @dpm_entry_num: index of this device in device persistent map table
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* @dev_handle: device handle for the device pointed by this entry
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*/
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struct map_removal_table{
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u16 dpm_entry_num;
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u16 dev_handle;
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};
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typedef struct mpr_fw_diagnostic_buffer {
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size_t size;
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uint8_t extended_type;
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uint8_t buffer_type;
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uint8_t force_release;
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uint32_t product_specific[23];
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uint8_t immediate;
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uint8_t enabled;
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uint8_t valid_data;
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uint8_t owned_by_firmware;
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uint32_t unique_id;
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} mpr_fw_diagnostic_buffer_t;
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struct mpr_softc;
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struct mpr_command;
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struct mprsas_softc;
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union ccb;
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struct mprsas_target;
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struct mpr_column_map;
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MALLOC_DECLARE(M_MPR);
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typedef void mpr_evt_callback_t(struct mpr_softc *, uintptr_t,
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MPI2_EVENT_NOTIFICATION_REPLY *reply);
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typedef void mpr_command_callback_t(struct mpr_softc *, struct mpr_command *cm);
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struct mpr_chain {
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TAILQ_ENTRY(mpr_chain) chain_link;
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void *chain;
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uint64_t chain_busaddr;
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};
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struct mpr_prp_page {
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TAILQ_ENTRY(mpr_prp_page) prp_page_link;
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uint64_t *prp_page;
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uint64_t prp_page_busaddr;
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};
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/*
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* This needs to be at least 2 to support SMP passthrough.
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*/
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#define MPR_IOVEC_COUNT 2
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struct mpr_command {
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TAILQ_ENTRY(mpr_command) cm_link;
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TAILQ_ENTRY(mpr_command) cm_recovery;
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struct mpr_softc *cm_sc;
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union ccb *cm_ccb;
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void *cm_data;
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u_int cm_length;
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u_int cm_out_len;
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struct uio cm_uio;
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struct iovec cm_iovec[MPR_IOVEC_COUNT];
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u_int cm_max_segs;
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u_int cm_sglsize;
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void *cm_sge;
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uint8_t *cm_req;
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uint8_t *cm_reply;
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uint32_t cm_reply_data;
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mpr_command_callback_t *cm_complete;
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void *cm_complete_data;
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struct mprsas_target *cm_targ;
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MPI2_REQUEST_DESCRIPTOR_UNION cm_desc;
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u_int cm_lun;
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u_int cm_flags;
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#define MPR_CM_FLAGS_POLLED (1 << 0)
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#define MPR_CM_FLAGS_COMPLETE (1 << 1)
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#define MPR_CM_FLAGS_SGE_SIMPLE (1 << 2)
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#define MPR_CM_FLAGS_DATAOUT (1 << 3)
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#define MPR_CM_FLAGS_DATAIN (1 << 4)
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#define MPR_CM_FLAGS_WAKEUP (1 << 5)
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#define MPR_CM_FLAGS_USE_UIO (1 << 6)
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#define MPR_CM_FLAGS_SMP_PASS (1 << 7)
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#define MPR_CM_FLAGS_CHAIN_FAILED (1 << 8)
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#define MPR_CM_FLAGS_ERROR_MASK MPR_CM_FLAGS_CHAIN_FAILED
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#define MPR_CM_FLAGS_USE_CCB (1 << 9)
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#define MPR_CM_FLAGS_SATA_ID_TIMEOUT (1 << 10)
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u_int cm_state;
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#define MPR_CM_STATE_FREE 0
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#define MPR_CM_STATE_BUSY 1
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#define MPR_CM_STATE_TIMEDOUT 2
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bus_dmamap_t cm_dmamap;
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struct scsi_sense_data *cm_sense;
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uint64_t *nvme_error_response;
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TAILQ_HEAD(, mpr_chain) cm_chain_list;
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TAILQ_HEAD(, mpr_prp_page) cm_prp_page_list;
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uint32_t cm_req_busaddr;
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bus_addr_t cm_sense_busaddr;
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struct callout cm_callout;
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};
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struct mpr_column_map {
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uint16_t dev_handle;
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uint8_t phys_disk_num;
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};
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struct mpr_event_handle {
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TAILQ_ENTRY(mpr_event_handle) eh_list;
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mpr_evt_callback_t *callback;
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void *data;
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uint8_t mask[16];
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};
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struct mpr_queue {
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struct mpr_softc *sc;
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int qnum;
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MPI2_REPLY_DESCRIPTORS_UNION *post_queue;
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int replypostindex;
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#ifdef notyet
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ck_ring_buffer_t *ringmem;
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ck_ring_buffer_t *chainmem;
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ck_ring_t req_ring;
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ck_ring_t chain_ring;
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#endif
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bus_dma_tag_t buffer_dmat;
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int io_cmds_highwater;
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int chain_free_lowwater;
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int chain_alloc_fail;
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struct resource *irq;
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void *intrhand;
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int irq_rid;
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};
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struct mpr_softc {
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device_t mpr_dev;
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struct cdev *mpr_cdev;
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u_int mpr_flags;
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#define MPR_FLAGS_INTX (1 << 0)
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#define MPR_FLAGS_MSI (1 << 1)
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#define MPR_FLAGS_BUSY (1 << 2)
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#define MPR_FLAGS_SHUTDOWN (1 << 3)
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#define MPR_FLAGS_DIAGRESET (1 << 4)
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#define MPR_FLAGS_ATTACH_DONE (1 << 5)
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#define MPR_FLAGS_GEN35_IOC (1 << 6)
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#define MPR_FLAGS_REALLOCATED (1 << 7)
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u_int mpr_debug;
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int msi_msgs;
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u_int atomic_desc_capable;
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int tm_cmds_active;
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int io_cmds_active;
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int io_cmds_highwater;
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int chain_free;
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int max_chains;
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int max_io_pages;
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u_int maxio;
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int chain_free_lowwater;
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uint32_t chain_frame_size;
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uint16_t chain_seg_size;
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int prp_buffer_size;
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int prp_pages_free;
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int prp_pages_free_lowwater;
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u_int enable_ssu;
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int spinup_wait_time;
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int use_phynum;
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uint64_t chain_alloc_fail;
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uint64_t prp_page_alloc_fail;
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struct sysctl_ctx_list sysctl_ctx;
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struct sysctl_oid *sysctl_tree;
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char fw_version[16];
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struct mpr_command *commands;
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struct mpr_chain *chains;
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struct mpr_prp_page *prps;
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struct callout periodic;
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struct callout device_check_callout;
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struct mpr_queue *queues;
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struct mprsas_softc *sassc;
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TAILQ_HEAD(, mpr_command) req_list;
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TAILQ_HEAD(, mpr_command) high_priority_req_list;
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TAILQ_HEAD(, mpr_chain) chain_list;
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TAILQ_HEAD(, mpr_prp_page) prp_page_list;
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TAILQ_HEAD(, mpr_command) tm_list;
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int replypostindex;
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int replyfreeindex;
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struct resource *mpr_regs_resource;
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bus_space_handle_t mpr_bhandle;
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bus_space_tag_t mpr_btag;
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int mpr_regs_rid;
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bus_dma_tag_t mpr_parent_dmat;
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bus_dma_tag_t buffer_dmat;
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MPI2_IOC_FACTS_REPLY *facts;
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int num_reqs;
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int num_replies;
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int fqdepth; /* Free queue */
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int pqdepth; /* Post queue */
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uint8_t event_mask[16];
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TAILQ_HEAD(, mpr_event_handle) event_list;
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struct mpr_event_handle *mpr_log_eh;
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struct mtx mpr_mtx;
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struct intr_config_hook mpr_ich;
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uint8_t *req_frames;
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bus_addr_t req_busaddr;
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bus_dma_tag_t req_dmat;
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bus_dmamap_t req_map;
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uint8_t *reply_frames;
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bus_addr_t reply_busaddr;
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bus_dma_tag_t reply_dmat;
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bus_dmamap_t reply_map;
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struct scsi_sense_data *sense_frames;
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bus_addr_t sense_busaddr;
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bus_dma_tag_t sense_dmat;
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bus_dmamap_t sense_map;
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uint8_t *chain_frames;
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bus_addr_t chain_busaddr;
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bus_dma_tag_t chain_dmat;
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bus_dmamap_t chain_map;
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uint8_t *prp_pages;
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bus_addr_t prp_page_busaddr;
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bus_dma_tag_t prp_page_dmat;
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bus_dmamap_t prp_page_map;
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MPI2_REPLY_DESCRIPTORS_UNION *post_queue;
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bus_addr_t post_busaddr;
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uint32_t *free_queue;
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bus_addr_t free_busaddr;
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bus_dma_tag_t queues_dmat;
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bus_dmamap_t queues_map;
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uint8_t *fw_diag_buffer;
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bus_addr_t fw_diag_busaddr;
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bus_dma_tag_t fw_diag_dmat;
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bus_dmamap_t fw_diag_map;
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uint8_t ir_firmware;
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/* static config pages */
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Mpi2IOCPage8_t ioc_pg8;
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Mpi2IOUnitPage8_t iounit_pg8;
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/* host mapping support */
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struct dev_mapping_table *mapping_table;
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struct enc_mapping_table *enclosure_table;
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struct map_removal_table *removal_table;
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uint8_t *dpm_entry_used;
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uint8_t *dpm_flush_entry;
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Mpi2DriverMappingPage0_t *dpm_pg0;
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uint16_t max_devices;
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uint16_t max_enclosures;
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uint16_t max_expanders;
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uint8_t max_volumes;
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uint8_t num_enc_table_entries;
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uint8_t num_rsvd_entries;
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uint16_t max_dpm_entries;
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uint8_t is_dpm_enable;
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uint8_t track_mapping_events;
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uint32_t pending_map_events;
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/* FW diag Buffer List */
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mpr_fw_diagnostic_buffer_t
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fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
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/* Event Recording IOCTL support */
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uint32_t events_to_record[4];
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mpr_event_entry_t recorded_events[MPR_EVENT_QUEUE_SIZE];
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uint8_t event_index;
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uint32_t event_number;
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/* EEDP and TLR support */
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uint8_t eedp_enabled;
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uint8_t control_TLR;
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/* Shutdown Event Handler */
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eventhandler_tag shutdown_eh;
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/* To track topo events during reset */
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#define MPR_DIAG_RESET_TIMEOUT 300000
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uint8_t wait_for_port_enable;
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uint8_t port_enable_complete;
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uint8_t msleep_fake_chan;
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/* StartStopUnit command handling at shutdown */
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uint32_t SSU_refcount;
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uint8_t SSU_started;
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/* Configuration tunables */
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u_int disable_msix;
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u_int disable_msi;
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u_int max_msix;
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u_int max_reqframes;
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u_int max_prireqframes;
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u_int max_replyframes;
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u_int max_evtframes;
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char exclude_ids[80];
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struct timeval lastfail;
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};
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struct mpr_config_params {
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MPI2_CONFIG_EXT_PAGE_HEADER_UNION hdr;
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u_int action;
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u_int page_address; /* Attributes, not a phys address */
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u_int status;
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void *buffer;
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u_int length;
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int timeout;
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void (*callback)(struct mpr_softc *, struct mpr_config_params *);
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void *cbdata;
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};
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struct scsi_read_capacity_eedp
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{
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uint8_t addr[8];
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uint8_t length[4];
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uint8_t protect;
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};
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static __inline uint32_t
|
|
mpr_regread(struct mpr_softc *sc, uint32_t offset)
|
|
{
|
|
return (bus_space_read_4(sc->mpr_btag, sc->mpr_bhandle, offset));
|
|
}
|
|
|
|
static __inline void
|
|
mpr_regwrite(struct mpr_softc *sc, uint32_t offset, uint32_t val)
|
|
{
|
|
bus_space_write_4(sc->mpr_btag, sc->mpr_bhandle, offset, val);
|
|
}
|
|
|
|
/* free_queue must have Little Endian address
|
|
* TODO- cm_reply_data is unwanted. We can remove it.
|
|
* */
|
|
static __inline void
|
|
mpr_free_reply(struct mpr_softc *sc, uint32_t busaddr)
|
|
{
|
|
if (++sc->replyfreeindex >= sc->fqdepth)
|
|
sc->replyfreeindex = 0;
|
|
sc->free_queue[sc->replyfreeindex] = htole32(busaddr);
|
|
mpr_regwrite(sc, MPI2_REPLY_FREE_HOST_INDEX_OFFSET, sc->replyfreeindex);
|
|
}
|
|
|
|
static __inline struct mpr_chain *
|
|
mpr_alloc_chain(struct mpr_softc *sc)
|
|
{
|
|
struct mpr_chain *chain;
|
|
|
|
if ((chain = TAILQ_FIRST(&sc->chain_list)) != NULL) {
|
|
TAILQ_REMOVE(&sc->chain_list, chain, chain_link);
|
|
sc->chain_free--;
|
|
if (sc->chain_free < sc->chain_free_lowwater)
|
|
sc->chain_free_lowwater = sc->chain_free;
|
|
} else
|
|
sc->chain_alloc_fail++;
|
|
return (chain);
|
|
}
|
|
|
|
static __inline void
|
|
mpr_free_chain(struct mpr_softc *sc, struct mpr_chain *chain)
|
|
{
|
|
#if 0
|
|
bzero(chain->chain, 128);
|
|
#endif
|
|
sc->chain_free++;
|
|
TAILQ_INSERT_TAIL(&sc->chain_list, chain, chain_link);
|
|
}
|
|
|
|
static __inline struct mpr_prp_page *
|
|
mpr_alloc_prp_page(struct mpr_softc *sc)
|
|
{
|
|
struct mpr_prp_page *prp_page;
|
|
|
|
if ((prp_page = TAILQ_FIRST(&sc->prp_page_list)) != NULL) {
|
|
TAILQ_REMOVE(&sc->prp_page_list, prp_page, prp_page_link);
|
|
sc->prp_pages_free--;
|
|
if (sc->prp_pages_free < sc->prp_pages_free_lowwater)
|
|
sc->prp_pages_free_lowwater = sc->prp_pages_free;
|
|
} else
|
|
sc->prp_page_alloc_fail++;
|
|
return (prp_page);
|
|
}
|
|
|
|
static __inline void
|
|
mpr_free_prp_page(struct mpr_softc *sc, struct mpr_prp_page *prp_page)
|
|
{
|
|
sc->prp_pages_free++;
|
|
TAILQ_INSERT_TAIL(&sc->prp_page_list, prp_page, prp_page_link);
|
|
}
|
|
|
|
static __inline void
|
|
mpr_free_command(struct mpr_softc *sc, struct mpr_command *cm)
|
|
{
|
|
struct mpr_chain *chain, *chain_temp;
|
|
struct mpr_prp_page *prp_page, *prp_page_temp;
|
|
|
|
if (cm->cm_reply != NULL)
|
|
mpr_free_reply(sc, cm->cm_reply_data);
|
|
cm->cm_reply = NULL;
|
|
cm->cm_flags = 0;
|
|
cm->cm_complete = NULL;
|
|
cm->cm_complete_data = NULL;
|
|
cm->cm_ccb = NULL;
|
|
cm->cm_targ = NULL;
|
|
cm->cm_max_segs = 0;
|
|
cm->cm_lun = 0;
|
|
cm->cm_state = MPR_CM_STATE_FREE;
|
|
cm->cm_data = NULL;
|
|
cm->cm_length = 0;
|
|
cm->cm_out_len = 0;
|
|
cm->cm_sglsize = 0;
|
|
cm->cm_sge = NULL;
|
|
|
|
TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, chain_temp) {
|
|
TAILQ_REMOVE(&cm->cm_chain_list, chain, chain_link);
|
|
mpr_free_chain(sc, chain);
|
|
}
|
|
TAILQ_FOREACH_SAFE(prp_page, &cm->cm_prp_page_list, prp_page_link,
|
|
prp_page_temp) {
|
|
TAILQ_REMOVE(&cm->cm_prp_page_list, prp_page, prp_page_link);
|
|
mpr_free_prp_page(sc, prp_page);
|
|
}
|
|
TAILQ_INSERT_TAIL(&sc->req_list, cm, cm_link);
|
|
}
|
|
|
|
static __inline struct mpr_command *
|
|
mpr_alloc_command(struct mpr_softc *sc)
|
|
{
|
|
struct mpr_command *cm;
|
|
|
|
cm = TAILQ_FIRST(&sc->req_list);
|
|
if (cm == NULL)
|
|
return (NULL);
|
|
|
|
TAILQ_REMOVE(&sc->req_list, cm, cm_link);
|
|
KASSERT(cm->cm_state == MPR_CM_STATE_FREE, ("mpr: Allocating busy "
|
|
"command\n"));
|
|
cm->cm_state = MPR_CM_STATE_BUSY;
|
|
return (cm);
|
|
}
|
|
|
|
static __inline void
|
|
mpr_free_high_priority_command(struct mpr_softc *sc, struct mpr_command *cm)
|
|
{
|
|
struct mpr_chain *chain, *chain_temp;
|
|
|
|
if (cm->cm_reply != NULL)
|
|
mpr_free_reply(sc, cm->cm_reply_data);
|
|
cm->cm_reply = NULL;
|
|
cm->cm_flags = 0;
|
|
cm->cm_complete = NULL;
|
|
cm->cm_complete_data = NULL;
|
|
cm->cm_ccb = NULL;
|
|
cm->cm_targ = NULL;
|
|
cm->cm_lun = 0;
|
|
cm->cm_state = MPR_CM_STATE_FREE;
|
|
TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, chain_temp) {
|
|
TAILQ_REMOVE(&cm->cm_chain_list, chain, chain_link);
|
|
mpr_free_chain(sc, chain);
|
|
}
|
|
TAILQ_INSERT_TAIL(&sc->high_priority_req_list, cm, cm_link);
|
|
}
|
|
|
|
static __inline struct mpr_command *
|
|
mpr_alloc_high_priority_command(struct mpr_softc *sc)
|
|
{
|
|
struct mpr_command *cm;
|
|
|
|
cm = TAILQ_FIRST(&sc->high_priority_req_list);
|
|
if (cm == NULL)
|
|
return (NULL);
|
|
|
|
TAILQ_REMOVE(&sc->high_priority_req_list, cm, cm_link);
|
|
KASSERT(cm->cm_state == MPR_CM_STATE_FREE, ("mpr: Allocating busy "
|
|
"command\n"));
|
|
cm->cm_state = MPR_CM_STATE_BUSY;
|
|
return (cm);
|
|
}
|
|
|
|
static __inline void
|
|
mpr_lock(struct mpr_softc *sc)
|
|
{
|
|
mtx_lock(&sc->mpr_mtx);
|
|
}
|
|
|
|
static __inline void
|
|
mpr_unlock(struct mpr_softc *sc)
|
|
{
|
|
mtx_unlock(&sc->mpr_mtx);
|
|
}
|
|
|
|
#define MPR_INFO (1 << 0) /* Basic info */
|
|
#define MPR_FAULT (1 << 1) /* Hardware faults */
|
|
#define MPR_EVENT (1 << 2) /* Event data from the controller */
|
|
#define MPR_LOG (1 << 3) /* Log data from the controller */
|
|
#define MPR_RECOVERY (1 << 4) /* Command error recovery tracing */
|
|
#define MPR_ERROR (1 << 5) /* Parameter errors, programming bugs */
|
|
#define MPR_INIT (1 << 6) /* Things related to system init */
|
|
#define MPR_XINFO (1 << 7) /* More detailed/noisy info */
|
|
#define MPR_USER (1 << 8) /* Trace user-generated commands */
|
|
#define MPR_MAPPING (1 << 9) /* Trace device mappings */
|
|
#define MPR_TRACE (1 << 10) /* Function-by-function trace */
|
|
|
|
#define MPR_SSU_DISABLE_SSD_DISABLE_HDD 0
|
|
#define MPR_SSU_ENABLE_SSD_DISABLE_HDD 1
|
|
#define MPR_SSU_DISABLE_SSD_ENABLE_HDD 2
|
|
#define MPR_SSU_ENABLE_SSD_ENABLE_HDD 3
|
|
|
|
#define mpr_printf(sc, args...) \
|
|
device_printf((sc)->mpr_dev, ##args)
|
|
|
|
#define mpr_print_field(sc, msg, args...) \
|
|
printf("\t" msg, ##args)
|
|
|
|
#define mpr_vprintf(sc, args...) \
|
|
do { \
|
|
if (bootverbose) \
|
|
mpr_printf(sc, ##args); \
|
|
} while (0)
|
|
|
|
#define mpr_dprint(sc, level, msg, args...) \
|
|
do { \
|
|
if ((sc)->mpr_debug & (level)) \
|
|
device_printf((sc)->mpr_dev, msg, ##args); \
|
|
} while (0)
|
|
|
|
#define MPR_PRINTFIELD_START(sc, tag...) \
|
|
mpr_printf((sc), ##tag); \
|
|
mpr_print_field((sc), ":\n")
|
|
#define MPR_PRINTFIELD_END(sc, tag) \
|
|
mpr_printf((sc), tag "\n")
|
|
#define MPR_PRINTFIELD(sc, facts, attr, fmt) \
|
|
mpr_print_field((sc), #attr ": " #fmt "\n", (facts)->attr)
|
|
|
|
static __inline void
|
|
mpr_from_u64(uint64_t data, U64 *mpr)
|
|
{
|
|
(mpr)->High = htole32((uint32_t)((data) >> 32));
|
|
(mpr)->Low = htole32((uint32_t)((data) & 0xffffffff));
|
|
}
|
|
|
|
static __inline uint64_t
|
|
mpr_to_u64(U64 *data)
|
|
{
|
|
return (((uint64_t)le32toh(data->High) << 32) | le32toh(data->Low));
|
|
}
|
|
|
|
static __inline void
|
|
mpr_mask_intr(struct mpr_softc *sc)
|
|
{
|
|
uint32_t mask;
|
|
|
|
mask = mpr_regread(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET);
|
|
mask |= MPI2_HIM_REPLY_INT_MASK;
|
|
mpr_regwrite(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET, mask);
|
|
}
|
|
|
|
static __inline void
|
|
mpr_unmask_intr(struct mpr_softc *sc)
|
|
{
|
|
uint32_t mask;
|
|
|
|
mask = mpr_regread(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET);
|
|
mask &= ~MPI2_HIM_REPLY_INT_MASK;
|
|
mpr_regwrite(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET, mask);
|
|
}
|
|
|
|
int mpr_pci_setup_interrupts(struct mpr_softc *sc);
|
|
void mpr_pci_free_interrupts(struct mpr_softc *sc);
|
|
int mpr_pci_restore(struct mpr_softc *sc);
|
|
|
|
void mpr_get_tunables(struct mpr_softc *sc);
|
|
int mpr_attach(struct mpr_softc *sc);
|
|
int mpr_free(struct mpr_softc *sc);
|
|
void mpr_intr(void *);
|
|
void mpr_intr_msi(void *);
|
|
void mpr_intr_locked(void *);
|
|
int mpr_register_events(struct mpr_softc *, uint8_t *, mpr_evt_callback_t *,
|
|
void *, struct mpr_event_handle **);
|
|
int mpr_restart(struct mpr_softc *);
|
|
int mpr_update_events(struct mpr_softc *, struct mpr_event_handle *, uint8_t *);
|
|
int mpr_deregister_events(struct mpr_softc *, struct mpr_event_handle *);
|
|
void mpr_build_nvme_prp(struct mpr_softc *sc, struct mpr_command *cm,
|
|
Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, void *data,
|
|
uint32_t data_in_sz, uint32_t data_out_sz);
|
|
int mpr_push_sge(struct mpr_command *, MPI2_SGE_SIMPLE64 *, size_t, int);
|
|
int mpr_push_ieee_sge(struct mpr_command *, void *, int);
|
|
int mpr_add_dmaseg(struct mpr_command *, vm_paddr_t, size_t, u_int, int);
|
|
int mpr_attach_sas(struct mpr_softc *sc);
|
|
int mpr_detach_sas(struct mpr_softc *sc);
|
|
int mpr_read_config_page(struct mpr_softc *, struct mpr_config_params *);
|
|
int mpr_write_config_page(struct mpr_softc *, struct mpr_config_params *);
|
|
void mpr_memaddr_cb(void *, bus_dma_segment_t *, int , int );
|
|
void mpr_init_sge(struct mpr_command *cm, void *req, void *sge);
|
|
int mpr_attach_user(struct mpr_softc *);
|
|
void mpr_detach_user(struct mpr_softc *);
|
|
void mprsas_record_event(struct mpr_softc *sc,
|
|
MPI2_EVENT_NOTIFICATION_REPLY *event_reply);
|
|
|
|
int mpr_map_command(struct mpr_softc *sc, struct mpr_command *cm);
|
|
int mpr_wait_command(struct mpr_softc *sc, struct mpr_command **cm, int timeout,
|
|
int sleep_flag);
|
|
int mpr_request_polled(struct mpr_softc *sc, struct mpr_command **cm);
|
|
|
|
int mpr_config_get_bios_pg3(struct mpr_softc *sc, Mpi2ConfigReply_t
|
|
*mpi_reply, Mpi2BiosPage3_t *config_page);
|
|
int mpr_config_get_raid_volume_pg0(struct mpr_softc *sc, Mpi2ConfigReply_t
|
|
*mpi_reply, Mpi2RaidVolPage0_t *config_page, u32 page_address);
|
|
int mpr_config_get_ioc_pg8(struct mpr_softc *sc, Mpi2ConfigReply_t *,
|
|
Mpi2IOCPage8_t *);
|
|
int mpr_config_get_iounit_pg8(struct mpr_softc *sc,
|
|
Mpi2ConfigReply_t *mpi_reply, Mpi2IOUnitPage8_t *config_page);
|
|
int mpr_config_get_sas_device_pg0(struct mpr_softc *, Mpi2ConfigReply_t *,
|
|
Mpi2SasDevicePage0_t *, u32 , u16 );
|
|
int mpr_config_get_pcie_device_pg0(struct mpr_softc *sc, Mpi2ConfigReply_t
|
|
*mpi_reply, Mpi26PCIeDevicePage0_t *config_page, u32 form, u16 handle);
|
|
int mpr_config_get_pcie_device_pg2(struct mpr_softc *sc, Mpi2ConfigReply_t
|
|
*mpi_reply, Mpi26PCIeDevicePage2_t *config_page, u32 form, u16 handle);
|
|
int mpr_config_get_dpm_pg0(struct mpr_softc *, Mpi2ConfigReply_t *,
|
|
Mpi2DriverMappingPage0_t *, u16 );
|
|
int mpr_config_get_raid_volume_pg1(struct mpr_softc *sc,
|
|
Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage1_t *config_page, u32 form,
|
|
u16 handle);
|
|
int mpr_config_get_volume_wwid(struct mpr_softc *sc, u16 volume_handle,
|
|
u64 *wwid);
|
|
int mpr_config_get_raid_pd_pg0(struct mpr_softc *sc,
|
|
Mpi2ConfigReply_t *mpi_reply, Mpi2RaidPhysDiskPage0_t *config_page,
|
|
u32 page_address);
|
|
void mprsas_ir_shutdown(struct mpr_softc *sc);
|
|
|
|
int mpr_reinit(struct mpr_softc *sc);
|
|
void mprsas_handle_reinit(struct mpr_softc *sc);
|
|
|
|
void mpr_base_static_config_pages(struct mpr_softc *sc);
|
|
|
|
int mpr_mapping_initialize(struct mpr_softc *);
|
|
void mpr_mapping_topology_change_event(struct mpr_softc *,
|
|
Mpi2EventDataSasTopologyChangeList_t *);
|
|
void mpr_mapping_pcie_topology_change_event(struct mpr_softc *sc,
|
|
Mpi26EventDataPCIeTopologyChangeList_t *event_data);
|
|
void mpr_mapping_free_memory(struct mpr_softc *sc);
|
|
int mpr_config_set_dpm_pg0(struct mpr_softc *, Mpi2ConfigReply_t *,
|
|
Mpi2DriverMappingPage0_t *, u16 );
|
|
void mpr_mapping_exit(struct mpr_softc *);
|
|
void mpr_mapping_check_devices(void *);
|
|
int mpr_mapping_allocate_memory(struct mpr_softc *sc);
|
|
unsigned int mpr_mapping_get_tid(struct mpr_softc *, uint64_t , u16);
|
|
unsigned int mpr_mapping_get_tid_from_handle(struct mpr_softc *sc,
|
|
u16 handle);
|
|
unsigned int mpr_mapping_get_raid_tid(struct mpr_softc *sc, u64 wwid,
|
|
u16 volHandle);
|
|
unsigned int mpr_mapping_get_raid_tid_from_handle(struct mpr_softc *sc,
|
|
u16 volHandle);
|
|
void mpr_mapping_enclosure_dev_status_change_event(struct mpr_softc *,
|
|
Mpi2EventDataSasEnclDevStatusChange_t *event_data);
|
|
void mpr_mapping_ir_config_change_event(struct mpr_softc *sc,
|
|
Mpi2EventDataIrConfigChangeList_t *event_data);
|
|
|
|
void mprsas_evt_handler(struct mpr_softc *sc, uintptr_t data,
|
|
MPI2_EVENT_NOTIFICATION_REPLY *event);
|
|
void mprsas_prepare_remove(struct mprsas_softc *sassc, uint16_t handle);
|
|
void mprsas_prepare_volume_remove(struct mprsas_softc *sassc, uint16_t handle);
|
|
int mprsas_startup(struct mpr_softc *sc);
|
|
struct mprsas_target * mprsas_find_target_by_handle(struct mprsas_softc *, int,
|
|
uint16_t);
|
|
void mprsas_realloc_targets(struct mpr_softc *sc, int maxtargets);
|
|
struct mpr_command * mprsas_alloc_tm(struct mpr_softc *sc);
|
|
void mprsas_free_tm(struct mpr_softc *sc, struct mpr_command *tm);
|
|
void mprsas_release_simq_reinit(struct mprsas_softc *sassc);
|
|
int mprsas_send_reset(struct mpr_softc *sc, struct mpr_command *tm,
|
|
uint8_t type);
|
|
|
|
SYSCTL_DECL(_hw_mpr);
|
|
|
|
/* Compatibility shims for different OS versions */
|
|
#if __FreeBSD_version >= 800001
|
|
#define mpr_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
|
|
kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
|
|
#define mpr_kproc_exit(arg) kproc_exit(arg)
|
|
#else
|
|
#define mpr_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
|
|
kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
|
|
#define mpr_kproc_exit(arg) kthread_exit(arg)
|
|
#endif
|
|
|
|
#if defined(CAM_PRIORITY_XPT)
|
|
#define MPR_PRIORITY_XPT CAM_PRIORITY_XPT
|
|
#else
|
|
#define MPR_PRIORITY_XPT 5
|
|
#endif
|
|
|
|
#if __FreeBSD_version < 800107
|
|
// Prior to FreeBSD-8.0 scp3_flags was not defined.
|
|
#define spc3_flags reserved
|
|
|
|
#define SPC3_SID_PROTECT 0x01
|
|
#define SPC3_SID_3PC 0x08
|
|
#define SPC3_SID_TPGS_MASK 0x30
|
|
#define SPC3_SID_TPGS_IMPLICIT 0x10
|
|
#define SPC3_SID_TPGS_EXPLICIT 0x20
|
|
#define SPC3_SID_ACC 0x40
|
|
#define SPC3_SID_SCCS 0x80
|
|
|
|
#define CAM_PRIORITY_NORMAL CAM_PRIORITY_NONE
|
|
#endif
|
|
|
|
/* Definitions for SCSI unmap translation to NVMe DSM command */
|
|
|
|
/* UNMAP block descriptor structure */
|
|
struct unmap_blk_desc {
|
|
uint64_t slba;
|
|
uint32_t nlb;
|
|
uint32_t resv;
|
|
};
|
|
|
|
/* UNMAP command's data */
|
|
struct unmap_parm_list {
|
|
uint16_t unmap_data_len;
|
|
uint16_t unmap_blk_desc_data_len;
|
|
uint32_t resv;
|
|
struct unmap_blk_desc desc[0];
|
|
};
|
|
|
|
/* SCSI ADDITIONAL SENSE Codes */
|
|
#define FIXED_SENSE_DATA 0x70
|
|
#define SCSI_ASC_NO_SENSE 0x00
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#define SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT 0x03
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#define SCSI_ASC_LUN_NOT_READY 0x04
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#define SCSI_ASC_WARNING 0x0B
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#define SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED 0x10
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#define SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED 0x10
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#define SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED 0x10
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#define SCSI_ASC_UNRECOVERED_READ_ERROR 0x11
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#define SCSI_ASC_MISCOMPARE_DURING_VERIFY 0x1D
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#define SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID 0x20
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#define SCSI_ASC_ILLEGAL_COMMAND 0x20
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#define SCSI_ASC_ILLEGAL_BLOCK 0x21
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#define SCSI_ASC_INVALID_CDB 0x24
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#define SCSI_ASC_INVALID_LUN 0x25
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#define SCSI_ASC_INVALID_PARAMETER 0x26
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#define SCSI_ASC_FORMAT_COMMAND_FAILED 0x31
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#define SCSI_ASC_INTERNAL_TARGET_FAILURE 0x44
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/* SCSI ADDITIONAL SENSE Code Qualifiers */
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#define SCSI_ASCQ_CAUSE_NOT_REPORTABLE 0x00
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#define SCSI_ASCQ_FORMAT_COMMAND_FAILED 0x01
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#define SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED 0x01
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#define SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED 0x02
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#define SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED 0x03
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#define SCSI_ASCQ_FORMAT_IN_PROGRESS 0x04
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#define SCSI_ASCQ_POWER_LOSS_EXPECTED 0x08
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#define SCSI_ASCQ_INVALID_LUN_ID 0x09
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#endif
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