607 lines
22 KiB
C
607 lines
22 KiB
C
/*-
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* Copyright (c) 1999,2000 Michael Smith
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* Copyright (c) 2000 BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Copyright (c) 2002 Eric Moore
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* Copyright (c) 2002 LSI Logic Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The party using or redistributing the source code and binary forms
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* agrees to the disclaimer below and the terms and conditions set forth
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* herein.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*
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* $FreeBSD$
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*/
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/********************************************************************************
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********************************************************************************
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Driver parameters
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********************************************************************************
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********************************************************************************/
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/*
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* We could actually use all 17 segments, but using only 16 means that
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* each scatter/gather map is 128 bytes in size, and thus we don't have to worry about
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* maps crossing page boundaries.
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*
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* The AMI documentation says that the limit is 26. Unfortunately, there's no way to
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* cleanly fit more than 16 entries in without a page boundary. But is this a concern,
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* since we allocate the s/g maps contiguously anyway?
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*/
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/*
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* emoore - Oct 21, 2002
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* firmware doesn't have sglist boundary restrictions.
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* The sgelem can be set to 26
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*/
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#define AMR_NSEG 26
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#define AMR_MAXCMD 255 /* ident = 0 not allowed */
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#define AMR_LIMITCMD 120 /* maximum count of outstanding commands */
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#define AMR_MAXLD 40
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#define AMR_MAX_CHANNELS 8
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#define AMR_MAX_TARGETS 15
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#define AMR_MAX_LUNS 7
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#define AMR_MAX_SCSI_CMDS (15 * AMR_MAX_CHANNELS) /* one for every target? */
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#define AMR_MAX_CDB_LEN 0x0a
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#define AMR_MAX_EXTCDB_LEN 0x10
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#define AMR_MAX_REQ_SENSE_LEN 0x20
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#define AMR_BLKSIZE 512 /* constant for all controllers */
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/*
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* Perform at-startup board initialisation.
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* At this point in time, this code doesn't work correctly, so leave it disabled.
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*/
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/*#define AMR_BOARD_INIT*/
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/********************************************************************************
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********************************************************************************
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Interface Magic Numbers
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********************************************************************************
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********************************************************************************/
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/*
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* Mailbox commands
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*/
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#define AMR_CMD_LREAD 0x01
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#define AMR_CMD_LWRITE 0x02
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#define AMR_CMD_PASS 0x03
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#define AMR_CMD_EXT_ENQUIRY 0x04
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#define AMR_CMD_ENQUIRY 0x05
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#define AMR_CMD_FLUSH 0x0a
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#define AMR_CMD_EXT_ENQUIRY2 0x0c
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#define AMR_CONFIG_PRODINFO 0x0e
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#define AMR_CMD_GET_MACHINEID 0x36
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#define AMR_CMD_GET_INITIATOR 0x7d /* returns one byte */
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#define AMR_CMD_CONFIG 0xa1
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#define AMR_CONFIG_PRODUCT_INFO 0x0e
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#define AMR_CONFIG_ENQ3 0x0f
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#define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY 0x01
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#define AMR_CONFIG_ENQ3_SOLICITED_FULL 0x02
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#define AMR_CONFIG_ENQ3_UNSOLICITED 0x03
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#define AMR_CMD_EXTPASS 0xe3
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/*
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* Command results
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*/
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#define AMR_STATUS_SUCCESS 0x00
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#define AMR_STATUS_ABORTED 0x02
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#define AMR_STATUS_FAILED 0x80
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/*
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* Physical/logical drive states
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*/
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#define AMR_DRV_CURSTATE(x) ((x) & 0x0f)
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#define AMR_DRV_PREVSTATE(x) (((x) >> 4) & 0x0f)
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#define AMR_DRV_OFFLINE 0x00
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#define AMR_DRV_DEGRADED 0x01
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#define AMR_DRV_OPTIMAL 0x02
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#define AMR_DRV_ONLINE 0x03
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#define AMR_DRV_FAILED 0x04
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#define AMR_DRV_REBUILD 0x05
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#define AMR_DRV_HOTSPARE 0x06
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/*
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* Logical drive properties
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*/
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#define AMR_DRV_RAID_MASK 0x0f /* RAID level 0, 1, 3, 5, etc. */
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#define AMR_DRV_WRITEBACK 0x10 /* write-back enabled */
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#define AMR_DRV_READHEAD 0x20 /* readhead policy enabled */
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#define AMR_DRV_ADAPTIVE 0x40 /* adaptive I/O policy enabled */
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/*
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* Battery status
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*/
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#define AMR_BATT_MODULE_MISSING 0x01
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#define AMR_BATT_LOW_VOLTAGE 0x02
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#define AMR_BATT_TEMP_HIGH 0x04
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#define AMR_BATT_PACK_MISSING 0x08
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#define AMR_BATT_CHARGE_MASK 0x30
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#define AMR_BATT_CHARGE_DONE 0x00
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#define AMR_BATT_CHARGE_INPROG 0x10
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#define AMR_BATT_CHARGE_FAIL 0x20
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#define AMR_BATT_CYCLES_EXCEEDED 0x40
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/********************************************************************************
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********************************************************************************
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8LD Firmware Interface
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********************************************************************************
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********************************************************************************/
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/*
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* Array constraints
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*/
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#define AMR_8LD_MAXDRIVES 8
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#define AMR_8LD_MAXCHAN 5
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#define AMR_8LD_MAXTARG 15
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#define AMR_8LD_MAXPHYSDRIVES (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG)
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/*
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* Adapter Info structure
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*/
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struct amr_adapter_info
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{
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u_int8_t aa_maxio;
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u_int8_t aa_rebuild_rate;
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u_int8_t aa_maxtargchan;
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u_int8_t aa_channels;
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u_int8_t aa_firmware[4];
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u_int16_t aa_flashage;
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u_int8_t aa_chipsetvalue;
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u_int8_t aa_memorysize;
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u_int8_t aa_cacheflush;
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u_int8_t aa_bios[4];
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u_int8_t aa_boardtype;
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u_int8_t aa_scsisensealert;
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u_int8_t aa_writeconfigcount;
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u_int8_t aa_driveinsertioncount;
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u_int8_t aa_inserteddrive;
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u_int8_t aa_batterystatus;
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u_int8_t res1;
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} __packed;
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/*
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* Logical Drive info structure
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*/
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struct amr_logdrive_info
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{
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u_int8_t al_numdrives;
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u_int8_t res1[3];
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u_int32_t al_size[AMR_8LD_MAXDRIVES];
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u_int8_t al_properties[AMR_8LD_MAXDRIVES];
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u_int8_t al_state[AMR_8LD_MAXDRIVES];
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} __packed;
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/*
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* Physical Drive info structure
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*/
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struct amr_physdrive_info
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{
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u_int8_t ap_state[AMR_8LD_MAXPHYSDRIVES]; /* low nibble current state, high nibble previous state */
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u_int8_t ap_predictivefailure;
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} __packed;
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/*
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* Enquiry response structure for AMR_CMD_ENQUIRY, AMR_CMD_EXT_ENQUIRY and
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* AMR_CMD_EXT_ENQUIRY2.
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* ENQUIRY EXT_ENQUIRY EXT_ENQUIRY2
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*/
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struct amr_enquiry
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{
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struct amr_adapter_info ae_adapter; /* X X X */
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struct amr_logdrive_info ae_ldrv; /* X X X */
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struct amr_physdrive_info ae_pdrv; /* X X X */
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u_int8_t ae_formatting[AMR_8LD_MAXDRIVES];/* X X */
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u_int8_t res1[AMR_8LD_MAXDRIVES]; /* X X */
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u_int32_t ae_extlen; /* X */
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u_int16_t ae_subsystem; /* X */
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u_int16_t ae_subvendor; /* X */
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u_int32_t ae_signature; /* X */
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#define AMR_SIG_431 0xfffe0001
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#define AMR_SIG_438 0xfffd0002
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#define AMR_SIG_762 0xfffc0003
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#define AMR_SIG_T5 0xfffb0004
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#define AMR_SIG_466 0xfffa0005
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#define AMR_SIG_467 0xfff90006
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#define AMR_SIG_T7 0xfff80007
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#define AMR_SIG_490 0xfff70008
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u_int8_t res2[844]; /* X */
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} __packed;
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/********************************************************************************
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********************************************************************************
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40LD Firmware Interface
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********************************************************************************
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********************************************************************************/
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/*
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* Array constraints
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*/
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#define AMR_40LD_MAXDRIVES 40
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#define AMR_40LD_MAXCHAN 16
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#define AMR_40LD_MAXTARG 16
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#define AMR_40LD_MAXPHYSDRIVES 256
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/*
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* Product Info structure
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*/
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struct amr_prodinfo
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{
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u_int32_t ap_size; /* current size in bytes (not including resvd) */
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u_int32_t ap_configsig; /* default is 0x00282008, indicating 0x28 maximum
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* logical drives, 0x20 maximum stripes and 0x08
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* maximum spans */
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u_int8_t ap_firmware[16]; /* printable identifiers */
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u_int8_t ap_bios[16];
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u_int8_t ap_product[80];
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u_int8_t ap_maxio; /* maximum number of concurrent commands supported */
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u_int8_t ap_nschan; /* number of SCSI channels present */
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u_int8_t ap_fcloops; /* number of fibre loops present */
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u_int8_t ap_memtype; /* memory type */
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u_int32_t ap_signature;
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u_int16_t ap_memsize; /* onboard memory in MB */
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u_int16_t ap_subsystem; /* subsystem identifier */
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u_int16_t ap_subvendor; /* subsystem vendor ID */
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u_int8_t ap_numnotifyctr; /* number of notify counters */
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} __packed;
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/*
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* Notify structure
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*/
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struct amr_notify
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{
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u_int32_t an_globalcounter; /* change counter */
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u_int8_t an_paramcounter; /* parameter change counter */
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u_int8_t an_paramid;
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#define AMR_PARAM_REBUILD_RATE 0x01 /* value = new rebuild rate */
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#define AMR_PARAM_FLUSH_INTERVAL 0x02 /* value = new flush interval */
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#define AMR_PARAM_SENSE_ALERT 0x03 /* value = last physical drive with check condition set */
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#define AMR_PARAM_DRIVE_INSERTED 0x04 /* value = last physical drive inserted */
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#define AMR_PARAM_BATTERY_STATUS 0x05 /* value = battery status */
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u_int16_t an_paramval;
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u_int8_t an_writeconfigcounter; /* write config occurred */
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u_int8_t res1[3];
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u_int8_t an_ldrvopcounter; /* logical drive operation started/completed */
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u_int8_t an_ldrvopid;
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u_int8_t an_ldrvopcmd;
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#define AMR_LDRVOP_CHECK 0x01
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#define AMR_LDRVOP_INIT 0x02
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#define AMR_LDRVOP_REBUILD 0x03
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u_int8_t an_ldrvopstatus;
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#define AMR_LDRVOP_SUCCESS 0x00
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#define AMR_LDRVOP_FAILED 0x01
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#define AMR_LDRVOP_ABORTED 0x02
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#define AMR_LDRVOP_CORRECTED 0x03
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#define AMR_LDRVOP_STARTED 0x04
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u_int8_t an_ldrvstatecounter; /* logical drive state change occurred */
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u_int8_t an_ldrvstateid;
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u_int8_t an_ldrvstatenew;
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u_int8_t an_ldrvstateold;
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u_int8_t an_pdrvstatecounter; /* physical drive state change occurred */
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u_int8_t an_pdrvstateid;
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u_int8_t an_pdrvstatenew;
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u_int8_t an_pdrvstateold;
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u_int8_t an_pdrvfmtcounter;
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u_int8_t an_pdrvfmtid;
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u_int8_t an_pdrvfmtval;
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#define AMR_FORMAT_START 0x01
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#define AMR_FORMAT_COMPLETE 0x02
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u_int8_t res2;
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u_int8_t an_targxfercounter; /* scsi xfer rate change */
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u_int8_t an_targxferid;
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u_int8_t an_targxferval;
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u_int8_t res3;
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u_int8_t an_fcloopidcounter; /* FC/AL loop ID changed */
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u_int8_t an_fcloopidpdrvid;
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u_int8_t an_fcloopid0;
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u_int8_t an_fcloopid1;
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u_int8_t an_fcloopstatecounter; /* FC/AL loop status changed */
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u_int8_t an_fcloopstate0;
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u_int8_t an_fcloopstate1;
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u_int8_t res4;
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} __packed;
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/*
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* Enquiry3 structure
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*/
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struct amr_enquiry3
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{
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u_int32_t ae_datasize; /* valid data size in this structure */
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union { /* event notify structure */
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struct amr_notify n;
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u_int8_t pad[0x80];
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} ae_notify;
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u_int8_t ae_rebuildrate; /* current rebuild rate in % */
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u_int8_t ae_cacheflush; /* flush interval in seconds */
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u_int8_t ae_sensealert;
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u_int8_t ae_driveinsertcount; /* count of inserted drives */
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u_int8_t ae_batterystatus;
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u_int8_t ae_numldrives;
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u_int8_t ae_reconstate[AMR_40LD_MAXDRIVES / 8]; /* reconstruction state */
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u_int16_t ae_opstatus[AMR_40LD_MAXDRIVES / 8]; /* operation status per drive */
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u_int32_t ae_drivesize[AMR_40LD_MAXDRIVES]; /* logical drive size */
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u_int8_t ae_driveprop[AMR_40LD_MAXDRIVES]; /* logical drive properties */
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u_int8_t ae_drivestate[AMR_40LD_MAXDRIVES]; /* physical drive state */
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u_int16_t ae_driveformat[AMR_40LD_MAXPHYSDRIVES];
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u_int8_t ae_targxfer[80]; /* physical drive transfer rates */
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u_int8_t res1[263]; /* pad to 1024 bytes */
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} __packed;
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/********************************************************************************
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********************************************************************************
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Mailbox and Command Structures
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********************************************************************************
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********************************************************************************/
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#define AMR_MBOX_CMDSIZE 0x10 /* portion worth copying for controller */
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struct amr_mailbox
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{
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u_int8_t mb_command;
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u_int8_t mb_ident;
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u_int16_t mb_blkcount;
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u_int32_t mb_lba;
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u_int32_t mb_physaddr;
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u_int8_t mb_drive;
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u_int8_t mb_nsgelem;
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u_int8_t res1;
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u_int8_t mb_busy;
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u_int8_t mb_nstatus;
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u_int8_t mb_status;
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u_int8_t mb_completed[46];
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u_int8_t mb_poll;
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u_int8_t mb_ack;
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u_int8_t res2[16];
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} __packed;
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struct amr_mailbox64
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{
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u_int32_t mb64_segment; /* for 64-bit controllers */
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struct amr_mailbox mb;
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} __packed;
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struct amr_mailbox_ioctl
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{
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u_int8_t mb_command;
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u_int8_t mb_ident;
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u_int8_t mb_channel;
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u_int8_t mb_param;
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u_int8_t mb_pad[4];
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u_int32_t mb_physaddr;
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u_int8_t mb_drive;
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u_int8_t mb_nsgelem;
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u_int8_t res1;
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u_int8_t mb_busy;
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u_int8_t mb_nstatus;
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u_int8_t mb_completed[46];
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u_int8_t mb_poll;
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u_int8_t mb_ack;
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u_int8_t res4[16];
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} __packed;
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struct amr_sgentry
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{
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u_int32_t sg_addr;
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u_int32_t sg_count;
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} __packed;
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struct amr_passthrough
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{
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u_int8_t ap_timeout:3;
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u_int8_t ap_ars:1;
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u_int8_t ap_dummy:3;
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u_int8_t ap_islogical:1;
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u_int8_t ap_logical_drive_no;
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u_int8_t ap_channel;
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u_int8_t ap_scsi_id;
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u_int8_t ap_queue_tag;
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u_int8_t ap_queue_action;
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u_int8_t ap_cdb[AMR_MAX_CDB_LEN];
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u_int8_t ap_cdb_length;
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u_int8_t ap_request_sense_length;
|
|
u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN];
|
|
u_int8_t ap_no_sg_elements;
|
|
u_int8_t ap_scsi_status;
|
|
u_int32_t ap_data_transfer_address;
|
|
u_int32_t ap_data_transfer_length;
|
|
} __packed;
|
|
|
|
struct amr_ext_passthrough
|
|
{
|
|
u_int8_t ap_timeout:3;
|
|
u_int8_t ap_ars:1;
|
|
u_int8_t ap_rsvd1:1;
|
|
u_int8_t ap_cd_rom:1;
|
|
u_int8_t ap_rsvd2:1;
|
|
u_int8_t ap_islogical:1;
|
|
u_int8_t ap_logical_drive_no;
|
|
u_int8_t ap_channel;
|
|
u_int8_t ap_scsi_id;
|
|
u_int8_t ap_queue_tag;
|
|
u_int8_t ap_queue_action;
|
|
u_int8_t ap_cdb_length;
|
|
u_int8_t ap_rsvd3;
|
|
u_int8_t ap_cdb[AMR_MAX_EXTCDB_LEN];
|
|
u_int8_t ap_no_sg_elements;
|
|
u_int8_t ap_scsi_status;
|
|
u_int8_t ap_request_sense_length;
|
|
u_int8_t ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN];
|
|
u_int8_t ap_rsvd4;
|
|
u_int32_t ap_data_transfer_address;
|
|
u_int32_t ap_data_transfer_length;
|
|
} __packed;
|
|
|
|
#ifdef _KERNEL
|
|
/********************************************************************************
|
|
********************************************************************************
|
|
"Quartz" i960 PCI bridge interface
|
|
********************************************************************************
|
|
********************************************************************************/
|
|
|
|
#define AMR_CFG_SIG 0xa0 /* PCI config register for signature */
|
|
#define AMR_SIGNATURE_1 0xCCCC /* i960 signature (older adapters) */
|
|
#define AMR_SIGNATURE_2 0x3344 /* i960 signature (newer adapters) */
|
|
|
|
/*
|
|
* Doorbell registers
|
|
*/
|
|
#define AMR_QIDB 0x20
|
|
#define AMR_QODB 0x2c
|
|
#define AMR_QIDB_SUBMIT 0x00000001 /* mailbox ready for work */
|
|
#define AMR_QIDB_ACK 0x00000002 /* mailbox done */
|
|
#define AMR_QODB_READY 0x10001234 /* work ready to be processed */
|
|
|
|
/*
|
|
* Initialisation status
|
|
*/
|
|
#define AMR_QINIT_SCAN 0x01 /* init scanning drives */
|
|
#define AMR_QINIT_SCANINIT 0x02 /* init scanning initialising */
|
|
#define AMR_QINIT_FIRMWARE 0x03 /* init firmware initing */
|
|
#define AMR_QINIT_INPROG 0xdc /* init in progress */
|
|
#define AMR_QINIT_SPINUP 0x2c /* init spinning drives */
|
|
#define AMR_QINIT_NOMEM 0xac /* insufficient memory */
|
|
#define AMR_QINIT_CACHEFLUSH 0xbc /* init flushing cache */
|
|
#define AMR_QINIT_DONE 0x9c /* init successfully done */
|
|
|
|
/*
|
|
* I/O primitives
|
|
*/
|
|
#define AMR_QPUT_IDB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QIDB, val)
|
|
#define AMR_QGET_IDB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QIDB)
|
|
#define AMR_QPUT_ODB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QODB, val)
|
|
#define AMR_QGET_ODB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QODB)
|
|
|
|
#ifdef AMR_BOARD_INIT
|
|
#define AMR_QRESET(sc) \
|
|
do { \
|
|
pci_write_config((sc)->amr_dev, 0x40, pci_read_config((sc)->amr_dev, 0x40, 1) | 0x20, 1); \
|
|
pci_write_config((sc)->amr_dev, 0x64, 0x1122, 1); \
|
|
} while (0)
|
|
#define AMR_QGET_INITSTATUS(sc) pci_read_config((sc)->amr_dev, 0x9c, 1)
|
|
#define AMR_QGET_INITCHAN(sc) pci_read_config((sc)->amr_dev, 0x9f, 1)
|
|
#define AMR_QGET_INITTARG(sc) pci_read_config((sc)->amr_dev, 0x9e, 1)
|
|
#endif
|
|
|
|
/********************************************************************************
|
|
********************************************************************************
|
|
"Standard" old-style ASIC bridge interface
|
|
********************************************************************************
|
|
********************************************************************************/
|
|
|
|
/*
|
|
* I/O registers
|
|
*/
|
|
#define AMR_SCMD 0x10 /* command/ack register (write) */
|
|
#define AMR_SMBOX_BUSY 0x10 /* mailbox status (read) */
|
|
#define AMR_STOGGLE 0x11 /* interrupt enable bit here */
|
|
#define AMR_SMBOX_0 0x14 /* mailbox physical address low byte */
|
|
#define AMR_SMBOX_1 0x15
|
|
#define AMR_SMBOX_2 0x16
|
|
#define AMR_SMBOX_3 0x17 /* high byte */
|
|
#define AMR_SMBOX_ENABLE 0x18 /* atomic mailbox address enable */
|
|
#define AMR_SINTR 0x1a /* interrupt status */
|
|
|
|
/*
|
|
* I/O magic numbers
|
|
*/
|
|
#define AMR_SCMD_POST 0x10 /* -> SCMD to initiate action on mailbox */
|
|
#define AMR_SCMD_ACKINTR 0x08 /* -> SCMD to ack mailbox retrieved */
|
|
#define AMR_STOGL_IENABLE 0xc0 /* in STOGGLE */
|
|
#define AMR_SINTR_VALID 0x40 /* in SINTR */
|
|
#define AMR_SMBOX_BUSYFLAG 0x10 /* in SMBOX_BUSY */
|
|
#define AMR_SMBOX_ADDR 0x00 /* -> SMBOX_ENABLE */
|
|
|
|
/*
|
|
* Initialisation status
|
|
*/
|
|
#define AMR_SINIT_ABEND 0xee /* init abnormal terminated */
|
|
#define AMR_SINIT_NOMEM 0xca /* insufficient memory */
|
|
#define AMR_SINIT_CACHEFLUSH 0xbb /* firmware flushing cache */
|
|
#define AMR_SINIT_INPROG 0x11 /* init in progress */
|
|
#define AMR_SINIT_SPINUP 0x22 /* firmware spinning drives */
|
|
#define AMR_SINIT_DONE 0x99 /* init successfully done */
|
|
|
|
/*
|
|
* I/O primitives
|
|
*/
|
|
#define AMR_SPUT_ISTAT(sc, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SINTR, val)
|
|
#define AMR_SGET_ISTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SINTR)
|
|
#define AMR_SACK_INTERRUPT(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_ACKINTR)
|
|
#define AMR_SPOST_COMMAND(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_POST)
|
|
#define AMR_SGET_MBSTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_BUSY)
|
|
#define AMR_SENABLE_INTR(sc) \
|
|
bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \
|
|
bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) | AMR_STOGL_IENABLE)
|
|
#define AMR_SDISABLE_INTR(sc) \
|
|
bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \
|
|
bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) & ~AMR_STOGL_IENABLE)
|
|
#define AMR_SBYTE_SET(sc, reg, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, reg, val)
|
|
|
|
#ifdef AMR_BOARD_INIT
|
|
#define AMR_SRESET(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, 0, 0x80)
|
|
#define AMR_SGET_INITSTATUS(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE)
|
|
#define AMR_SGET_FAILDRIVE(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 1)
|
|
#define AMR_SGET_INITCHAN(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 2)
|
|
#define AMR_SGET_INITTARG(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 3)
|
|
#endif
|
|
|
|
#endif /* _KERNEL */
|