481dd885f8
adapter list still capable, but only PCI-E adapters are now enabled. The user can enable older PCI-X or PCI adapters using ifconfig. Secondly, Arthur Hartwig pointed out my MSI change was not working correctly, changed to something that now does. Thanks Arthur. There was also a fundamental bug in the 82575 MSIX code, the MSIX registers had to be mapped, opps :) Rubber-stamped by: Pdeuskar
425 lines
14 KiB
C
425 lines
14 KiB
C
/**************************************************************************
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Copyright (c) 2001-2007, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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***************************************************************************/
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/*$FreeBSD$*/
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#ifndef _EM_H_DEFINED_
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#define _EM_H_DEFINED_
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/* Tunables */
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/*
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* EM_TXD: Maximum number of Transmit Descriptors
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* Valid Range: 80-256 for 82542 and 82543-based adapters
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* 80-4096 for others
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* Default Value: 256
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* This value is the number of transmit descriptors allocated by the driver.
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* Increasing this value allows the driver to queue more transmits. Each
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* descriptor is 16 bytes.
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* Since TDLEN should be multiple of 128bytes, the number of transmit
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* desscriptors should meet the following condition.
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* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
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*/
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#define EM_MIN_TXD 80
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#define EM_MAX_TXD_82543 256
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#define EM_MAX_TXD 4096
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#define EM_DEFAULT_TXD EM_MAX_TXD_82543
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/*
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* EM_RXD - Maximum number of receive Descriptors
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* Valid Range: 80-256 for 82542 and 82543-based adapters
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* 80-4096 for others
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* Default Value: 256
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* This value is the number of receive descriptors allocated by the driver.
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* Increasing this value allows the driver to buffer more incoming packets.
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* Each descriptor is 16 bytes. A receive buffer is also allocated for each
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* descriptor. The maximum MTU size is 16110.
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* Since TDLEN should be multiple of 128bytes, the number of transmit
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* desscriptors should meet the following condition.
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* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
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*/
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#define EM_MIN_RXD 80
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#define EM_MAX_RXD_82543 256
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#define EM_MAX_RXD 4096
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#define EM_DEFAULT_RXD EM_MAX_RXD_82543
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/*
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* EM_TIDV - Transmit Interrupt Delay Value
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value delays the generation of transmit interrupts in units of
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* 1.024 microseconds. Transmit interrupt reduction can improve CPU
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* efficiency if properly tuned for specific network traffic. If the
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* system is reporting dropped transmits, this value may be set too high
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* causing the driver to run out of available transmit descriptors.
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*/
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#define EM_TIDV 64
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/*
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* EM_TADV - Transmit Absolute Interrupt Delay Value
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* (Not valid for 82542/82543/82544)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value, in units of 1.024 microseconds, limits the delay in which a
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* transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
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* this value ensures that an interrupt is generated after the initial
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* packet is sent on the wire within the set amount of time. Proper tuning,
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* along with EM_TIDV, may improve traffic throughput in specific
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* network conditions.
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*/
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#define EM_TADV 64
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/*
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* EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 0
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* This value delays the generation of receive interrupts in units of 1.024
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* microseconds. Receive interrupt reduction can improve CPU efficiency if
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* properly tuned for specific network traffic. Increasing this value adds
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* extra latency to frame reception and can end up decreasing the throughput
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* of TCP traffic. If the system is reporting dropped receives, this value
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* may be set too high, causing the driver to run out of available receive
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* descriptors.
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*
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* CAUTION: When setting EM_RDTR to a value other than 0, adapters
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* may hang (stop transmitting) under certain network conditions.
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* If this occurs a WATCHDOG message is logged in the system
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* event log. In addition, the controller is automatically reset,
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* restoring the network connection. To eliminate the potential
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* for the hang ensure that EM_RDTR is set to 0.
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*/
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#define EM_RDTR 0
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/*
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* Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value, in units of 1.024 microseconds, limits the delay in which a
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* receive interrupt is generated. Useful only if EM_RDTR is non-zero,
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* this value ensures that an interrupt is generated after the initial
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* packet is received within the set amount of time. Proper tuning,
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* along with EM_RDTR, may improve traffic throughput in specific network
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* conditions.
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*/
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#define EM_RADV 64
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/*
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* This parameter controls the duration of transmit watchdog timer.
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*/
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#define EM_TX_TIMEOUT 5 /* set to 5 seconds */
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/*
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* This parameter controls when the driver calls the routine to reclaim
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* transmit descriptors.
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*/
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#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
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#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
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/*
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* This parameter controls whether or not autonegotation is enabled.
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* 0 - Disable autonegotiation
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* 1 - Enable autonegotiation
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*/
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#define DO_AUTO_NEG 1
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/*
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* This parameter control whether or not the driver will wait for
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* autonegotiation to complete.
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* 1 - Wait for autonegotiation to complete
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* 0 - Don't wait for autonegotiation to complete
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*/
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#define WAIT_FOR_AUTO_NEG_DEFAULT 0
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/* Tunables -- End */
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#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
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ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
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ADVERTISE_1000_FULL)
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#define AUTO_ALL_MODES 0
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/* PHY master/slave setting */
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#define EM_MASTER_SLAVE e1000_ms_hw_default
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/*
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* Micellaneous constants
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*/
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#define EM_VENDOR_ID 0x8086
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#define EM_FLASH 0x0014
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#define EM_JUMBO_PBA 0x00000028
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#define EM_DEFAULT_PBA 0x00000030
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#define EM_SMARTSPEED_DOWNSHIFT 3
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#define EM_SMARTSPEED_MAX 15
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#define EM_MAX_INTR 10
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#define EM_TSO_SEG_SIZE 4096 /* Max dma seg size */
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#define MAX_NUM_MULTICAST_ADDRESSES 128
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#define PCI_ANY_ID (~0U)
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#define ETHER_ALIGN 2
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#define EM_TX_BUFFER_SIZE ((uint32_t) 1514)
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#define EM_FC_PAUSE_TIME 0x0680
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#define EM_EEPROM_APME 0x400;
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/*
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* TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
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* multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
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* also optimize cache line size effect. H/W supports up to cache line size 128.
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*/
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#define EM_DBA_ALIGN 128
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#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
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/* PCI Config defines */
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#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
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#define EM_BAR_TYPE_MASK 0x00000001
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#define EM_BAR_TYPE_MMEM 0x00000000
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#define EM_BAR_TYPE_IO 0x00000001
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#define EM_BAR_TYPE_FLASH 0x0014
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#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
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#define EM_BAR_MEM_TYPE_MASK 0x00000006
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#define EM_BAR_MEM_TYPE_32BIT 0x00000000
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#define EM_BAR_MEM_TYPE_64BIT 0x00000004
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#define EM_MSIX_BAR 3 /* On 82575 */
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/* Defines for printing debug information */
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#define DEBUG_INIT 0
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#define DEBUG_IOCTL 0
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#define DEBUG_HW 0
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#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
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#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
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#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
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#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
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#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
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#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
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#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
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#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
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#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
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#define EM_MAX_SCATTER 64
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#define EM_TSO_SIZE 65535 /* maxsize of a dma transfer */
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#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
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#define ETH_ZLEN 60
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#define ETH_ADDR_LEN 6
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#define CSUM_OFFLOAD 7 /* Offload bits in csum flags */
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struct adapter;
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struct em_int_delay_info {
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struct adapter *adapter; /* Back-pointer to the adapter struct */
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int offset; /* Register offset to read/write */
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int value; /* Current value in usecs */
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};
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/*
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* Bus dma allocation structure used by
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* e1000_dma_malloc and e1000_dma_free.
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*/
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struct em_dma_alloc {
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bus_addr_t dma_paddr;
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caddr_t dma_vaddr;
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bus_dma_tag_t dma_tag;
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bus_dmamap_t dma_map;
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bus_dma_segment_t dma_seg;
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int dma_nseg;
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};
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/* Our adapter structure */
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struct adapter {
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struct ifnet *ifp;
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struct e1000_hw hw;
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/* FreeBSD operating-system-specific structures. */
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struct e1000_osdep osdep;
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struct device *dev;
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struct resource *res_memory;
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struct resource *flash_mem;
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struct resource *msix_mem;
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struct resource *res_ioport;
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struct resource *res_interrupt;
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void *int_handler_tag;
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struct ifmedia media;
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struct callout timer;
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struct callout tx_fifo_timer;
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int watchdog_timer;
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int io_rid;
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int msi;
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int if_flags;
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struct mtx mtx;
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int em_insert_vlan_header;
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struct task link_task;
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struct task rxtx_task;
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struct taskqueue *tq; /* private task queue */
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/* Management and WOL features */
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int wol;
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int has_manage;
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/* Info about the board itself */
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uint32_t part_num;
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uint8_t link_active;
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uint16_t link_speed;
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uint16_t link_duplex;
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uint32_t smartspeed;
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struct em_int_delay_info tx_int_delay;
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struct em_int_delay_info tx_abs_int_delay;
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struct em_int_delay_info rx_int_delay;
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struct em_int_delay_info rx_abs_int_delay;
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/*
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* Transmit definitions
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*
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* We have an array of num_tx_desc descriptors (handled
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* by the controller) paired with an array of tx_buffers
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* (at tx_buffer_area).
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* The index of the next available descriptor is next_avail_tx_desc.
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* The number of remaining tx_desc is num_tx_desc_avail.
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*/
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struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
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struct e1000_tx_desc *tx_desc_base;
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uint32_t next_avail_tx_desc;
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uint32_t next_tx_to_clean;
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volatile uint16_t num_tx_desc_avail;
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uint16_t num_tx_desc;
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uint32_t txd_cmd;
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struct em_buffer *tx_buffer_area;
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bus_dma_tag_t txtag; /* dma tag for tx */
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uint32_t tx_tso; /* last tx was tso */
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/*
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* Transmit function pointer:
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* legacy or advanced (82575 and later)
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*/
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int (*em_xmit) (struct adapter *adapter, struct mbuf **m_headp);
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/*
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* Receive definitions
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*
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* we have an array of num_rx_desc rx_desc (handled by the
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* controller), and paired with an array of rx_buffers
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* (at rx_buffer_area).
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* The next pair to check on receive is at offset next_rx_desc_to_check
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*/
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struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
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struct e1000_rx_desc *rx_desc_base;
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uint32_t next_rx_desc_to_check;
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uint32_t rx_buffer_len;
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uint16_t num_rx_desc;
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int rx_process_limit;
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struct em_buffer *rx_buffer_area;
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bus_dma_tag_t rxtag;
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bus_dmamap_t rx_sparemap;
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/*
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* First/last mbuf pointers, for
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* collecting multisegment RX packets.
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*/
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struct mbuf *fmp;
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struct mbuf *lmp;
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/* Misc stats maintained by the driver */
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unsigned long dropped_pkts;
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unsigned long mbuf_alloc_failed;
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unsigned long mbuf_cluster_failed;
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unsigned long no_tx_desc_avail1;
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unsigned long no_tx_desc_avail2;
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unsigned long no_tx_map_avail;
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unsigned long no_tx_dma_setup;
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unsigned long watchdog_events;
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unsigned long rx_overruns;
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/* Used in for 82547 10Mb Half workaround */
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#define EM_PBA_BYTES_SHIFT 0xA
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#define EM_TX_HEAD_ADDR_SHIFT 7
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#define EM_PBA_TX_MASK 0xFFFF0000
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#define EM_FIFO_HDR 0x10
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#define EM_82547_PKT_THRESH 0x3e0
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uint32_t tx_fifo_size;
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uint32_t tx_fifo_head;
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uint32_t tx_fifo_head_addr;
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uint64_t tx_fifo_reset_cnt;
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uint64_t tx_fifo_wrk_cnt;
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uint32_t tx_head_addr;
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/* For 82544 PCIX Workaround */
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boolean_t pcix_82544;
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boolean_t in_detach;
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struct e1000_hw_stats stats;
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};
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/* ******************************************************************************
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* vendor_info_array
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*
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* This array contains the list of Subvendor/Subdevice IDs on which the driver
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* should load.
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*
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* ******************************************************************************/
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typedef struct _em_vendor_info_t {
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unsigned int vendor_id;
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unsigned int device_id;
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unsigned int subvendor_id;
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unsigned int subdevice_id;
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unsigned int index;
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} em_vendor_info_t;
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struct em_buffer {
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int next_eop; /* Index of the desc to watch */
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struct mbuf *m_head;
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bus_dmamap_t map; /* bus_dma map for packet */
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};
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/* For 82544 PCIX Workaround */
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typedef struct _ADDRESS_LENGTH_PAIR
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{
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uint64_t address;
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uint32_t length;
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} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
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typedef struct _DESCRIPTOR_PAIR
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{
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ADDRESS_LENGTH_PAIR descriptor[4];
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uint32_t elements;
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} DESC_ARRAY, *PDESC_ARRAY;
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#define EM_LOCK_INIT(_sc, _name) \
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mtx_init(&(_sc)->mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
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#define EM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
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#define EM_LOCK(_sc) mtx_lock(&(_sc)->mtx)
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#define EM_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
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#define EM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
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#endif /* _EM_H_DEFINED_ */
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