2069 lines
68 KiB
Plaintext
2069 lines
68 KiB
Plaintext
@section Relocations
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BFD maintains relocations in much the same way it maintains
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symbols: they are left alone until required, then read in
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en-masse and translated into an internal form. A common
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routine @code{bfd_perform_relocation} acts upon the
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canonical form to do the fixup.
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Relocations are maintained on a per section basis,
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while symbols are maintained on a per BFD basis.
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All that a back end has to do to fit the BFD interface is to create
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a @code{struct reloc_cache_entry} for each relocation
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in a particular section, and fill in the right bits of the structures.
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@menu
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* typedef arelent::
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* howto manager::
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@end menu
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@node typedef arelent, howto manager, Relocations, Relocations
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@subsection typedef arelent
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This is the structure of a relocation entry:
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@example
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typedef enum bfd_reloc_status
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@{
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/* No errors detected. */
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bfd_reloc_ok,
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/* The relocation was performed, but there was an overflow. */
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bfd_reloc_overflow,
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/* The address to relocate was not within the section supplied. */
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bfd_reloc_outofrange,
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/* Used by special functions. */
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bfd_reloc_continue,
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/* Unsupported relocation size requested. */
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bfd_reloc_notsupported,
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/* Unused. */
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bfd_reloc_other,
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/* The symbol to relocate against was undefined. */
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bfd_reloc_undefined,
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/* The relocation was performed, but may not be ok - presently
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generated only when linking i960 coff files with i960 b.out
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symbols. If this type is returned, the error_message argument
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to bfd_perform_relocation will be set. */
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bfd_reloc_dangerous
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@}
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bfd_reloc_status_type;
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typedef struct reloc_cache_entry
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@{
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/* A pointer into the canonical table of pointers. */
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struct bfd_symbol **sym_ptr_ptr;
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/* offset in section. */
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bfd_size_type address;
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/* addend for relocation value. */
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bfd_vma addend;
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/* Pointer to how to perform the required relocation. */
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reloc_howto_type *howto;
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@}
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arelent;
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@end example
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@strong{Description}@*
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Here is a description of each of the fields within an @code{arelent}:
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@itemize @bullet
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@item
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@code{sym_ptr_ptr}
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@end itemize
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The symbol table pointer points to a pointer to the symbol
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associated with the relocation request. It is the pointer
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into the table returned by the back end's
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@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is
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referenced through a pointer to a pointer so that tools like
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the linker can fix up all the symbols of the same name by
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modifying only one pointer. The relocation routine looks in
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the symbol and uses the base of the section the symbol is
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attached to and the value of the symbol as the initial
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relocation offset. If the symbol pointer is zero, then the
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section provided is looked up.
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@itemize @bullet
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@item
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@code{address}
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@end itemize
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The @code{address} field gives the offset in bytes from the base of
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the section data which owns the relocation record to the first
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byte of relocatable information. The actual data relocated
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will be relative to this point; for example, a relocation
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type which modifies the bottom two bytes of a four byte word
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would not touch the first byte pointed to in a big endian
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world.
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@itemize @bullet
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@item
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@code{addend}
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@end itemize
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The @code{addend} is a value provided by the back end to be added (!)
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to the relocation offset. Its interpretation is dependent upon
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the howto. For example, on the 68k the code:
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@example
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char foo[];
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main()
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@{
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return foo[0x12345678];
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@}
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@end example
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Could be compiled into:
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@example
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linkw fp,#-4
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moveb @@#12345678,d0
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extbl d0
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unlk fp
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rts
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@end example
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This could create a reloc pointing to @code{foo}, but leave the
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offset in the data, something like:
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@example
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RELOCATION RECORDS FOR [.text]:
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offset type value
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00000006 32 _foo
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00000000 4e56 fffc ; linkw fp,#-4
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00000004 1039 1234 5678 ; moveb @@#12345678,d0
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0000000a 49c0 ; extbl d0
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0000000c 4e5e ; unlk fp
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0000000e 4e75 ; rts
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@end example
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Using coff and an 88k, some instructions don't have enough
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space in them to represent the full address range, and
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pointers have to be loaded in two parts. So you'd get something like:
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@example
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or.u r13,r0,hi16(_foo+0x12345678)
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ld.b r2,r13,lo16(_foo+0x12345678)
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jmp r1
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@end example
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This should create two relocs, both pointing to @code{_foo}, and with
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0x12340000 in their addend field. The data would consist of:
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@example
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RELOCATION RECORDS FOR [.text]:
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offset type value
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00000002 HVRT16 _foo+0x12340000
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00000006 LVRT16 _foo+0x12340000
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00000000 5da05678 ; or.u r13,r0,0x5678
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00000004 1c4d5678 ; ld.b r2,r13,0x5678
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00000008 f400c001 ; jmp r1
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@end example
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The relocation routine digs out the value from the data, adds
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it to the addend to get the original offset, and then adds the
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value of @code{_foo}. Note that all 32 bits have to be kept around
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somewhere, to cope with carry from bit 15 to bit 16.
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One further example is the sparc and the a.out format. The
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sparc has a similar problem to the 88k, in that some
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instructions don't have room for an entire offset, but on the
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sparc the parts are created in odd sized lumps. The designers of
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the a.out format chose to not use the data within the section
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for storing part of the offset; all the offset is kept within
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the reloc. Anything in the data should be ignored.
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@example
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save %sp,-112,%sp
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sethi %hi(_foo+0x12345678),%g2
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ldsb [%g2+%lo(_foo+0x12345678)],%i0
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ret
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restore
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@end example
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Both relocs contain a pointer to @code{foo}, and the offsets
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contain junk.
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@example
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RELOCATION RECORDS FOR [.text]:
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offset type value
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00000004 HI22 _foo+0x12345678
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00000008 LO10 _foo+0x12345678
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00000000 9de3bf90 ; save %sp,-112,%sp
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00000004 05000000 ; sethi %hi(_foo+0),%g2
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00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
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0000000c 81c7e008 ; ret
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00000010 81e80000 ; restore
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@end example
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@itemize @bullet
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@item
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@code{howto}
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@end itemize
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The @code{howto} field can be imagined as a
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relocation instruction. It is a pointer to a structure which
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contains information on what to do with all of the other
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information in the reloc record and data section. A back end
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would normally have a relocation instruction set and turn
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relocations into pointers to the correct structure on input -
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but it would be possible to create each howto field on demand.
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@subsubsection @code{enum complain_overflow}
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Indicates what sort of overflow checking should be done when
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performing a relocation.
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@example
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enum complain_overflow
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@{
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/* Do not complain on overflow. */
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complain_overflow_dont,
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/* Complain if the bitfield overflows, whether it is considered
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as signed or unsigned. */
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complain_overflow_bitfield,
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/* Complain if the value overflows when considered as signed
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number. */
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complain_overflow_signed,
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/* Complain if the value overflows when considered as an
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unsigned number. */
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complain_overflow_unsigned
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@};
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@end example
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@subsubsection @code{reloc_howto_type}
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The @code{reloc_howto_type} is a structure which contains all the
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information that libbfd needs to know to tie up a back end's data.
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@example
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struct bfd_symbol; /* Forward declaration. */
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struct reloc_howto_struct
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@{
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/* The type field has mainly a documentary use - the back end can
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do what it wants with it, though normally the back end's
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external idea of what a reloc number is stored
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in this field. For example, a PC relative word relocation
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in a coff environment has the type 023 - because that's
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what the outside world calls a R_PCRWORD reloc. */
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unsigned int type;
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/* The value the final relocation is shifted right by. This drops
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unwanted data from the relocation. */
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unsigned int rightshift;
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/* The size of the item to be relocated. This is *not* a
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power-of-two measure. To get the number of bytes operated
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on by a type of relocation, use bfd_get_reloc_size. */
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int size;
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/* The number of bits in the item to be relocated. This is used
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when doing overflow checking. */
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unsigned int bitsize;
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/* Notes that the relocation is relative to the location in the
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data section of the addend. The relocation function will
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subtract from the relocation value the address of the location
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being relocated. */
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bfd_boolean pc_relative;
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/* The bit position of the reloc value in the destination.
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The relocated value is left shifted by this amount. */
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unsigned int bitpos;
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/* What type of overflow error should be checked for when
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relocating. */
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enum complain_overflow complain_on_overflow;
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/* If this field is non null, then the supplied function is
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called rather than the normal function. This allows really
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strange relocation methods to be accommodated (e.g., i960 callj
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instructions). */
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bfd_reloc_status_type (*special_function)
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(bfd *, arelent *, struct bfd_symbol *, void *, asection *,
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bfd *, char **);
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/* The textual name of the relocation type. */
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char *name;
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/* Some formats record a relocation addend in the section contents
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rather than with the relocation. For ELF formats this is the
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distinction between USE_REL and USE_RELA (though the code checks
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for USE_REL == 1/0). The value of this field is TRUE if the
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addend is recorded with the section contents; when performing a
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partial link (ld -r) the section contents (the data) will be
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modified. The value of this field is FALSE if addends are
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recorded with the relocation (in arelent.addend); when performing
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a partial link the relocation will be modified.
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All relocations for all ELF USE_RELA targets should set this field
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to FALSE (values of TRUE should be looked on with suspicion).
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However, the converse is not true: not all relocations of all ELF
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USE_REL targets set this field to TRUE. Why this is so is peculiar
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to each particular target. For relocs that aren't used in partial
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links (e.g. GOT stuff) it doesn't matter what this is set to. */
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bfd_boolean partial_inplace;
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/* src_mask selects the part of the instruction (or data) to be used
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in the relocation sum. If the target relocations don't have an
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addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
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dst_mask to extract the addend from the section contents. If
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relocations do have an addend in the reloc, eg. ELF USE_RELA, this
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field should be zero. Non-zero values for ELF USE_RELA targets are
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bogus as in those cases the value in the dst_mask part of the
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section contents should be treated as garbage. */
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bfd_vma src_mask;
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/* dst_mask selects which parts of the instruction (or data) are
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replaced with a relocated value. */
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bfd_vma dst_mask;
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/* When some formats create PC relative instructions, they leave
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the value of the pc of the place being relocated in the offset
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slot of the instruction, so that a PC relative relocation can
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be made just by adding in an ordinary offset (e.g., sun3 a.out).
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Some formats leave the displacement part of an instruction
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empty (e.g., m88k bcs); this flag signals the fact. */
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bfd_boolean pcrel_offset;
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@};
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@end example
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@findex The HOWTO Macro
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@subsubsection @code{The HOWTO Macro}
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@strong{Description}@*
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The HOWTO define is horrible and will go away.
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@example
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#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
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@{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @}
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@end example
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@strong{Description}@*
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And will be replaced with the totally magic way. But for the
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moment, we are compatible, so do it this way.
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@example
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#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
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HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
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NAME, FALSE, 0, 0, IN)
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@end example
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@strong{Description}@*
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This is used to fill in an empty howto entry in an array.
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@example
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#define EMPTY_HOWTO(C) \
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HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
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NULL, FALSE, 0, 0, FALSE)
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@end example
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@strong{Description}@*
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Helper routine to turn a symbol into a relocation value.
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@example
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#define HOWTO_PREPARE(relocation, symbol) \
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@{ \
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if (symbol != NULL) \
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@{ \
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if (bfd_is_com_section (symbol->section)) \
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@{ \
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relocation = 0; \
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@} \
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else \
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@{ \
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relocation = symbol->value; \
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@} \
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@} \
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@}
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@end example
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@findex bfd_get_reloc_size
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@subsubsection @code{bfd_get_reloc_size}
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@strong{Synopsis}
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@example
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unsigned int bfd_get_reloc_size (reloc_howto_type *);
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@end example
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@strong{Description}@*
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For a reloc_howto_type that operates on a fixed number of bytes,
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this returns the number of bytes operated on.
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@findex arelent_chain
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@subsubsection @code{arelent_chain}
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@strong{Description}@*
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How relocs are tied together in an @code{asection}:
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@example
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typedef struct relent_chain
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@{
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arelent relent;
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struct relent_chain *next;
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@}
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arelent_chain;
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@end example
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@findex bfd_check_overflow
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@subsubsection @code{bfd_check_overflow}
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@strong{Synopsis}
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@example
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bfd_reloc_status_type bfd_check_overflow
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(enum complain_overflow how,
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unsigned int bitsize,
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unsigned int rightshift,
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unsigned int addrsize,
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bfd_vma relocation);
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@end example
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@strong{Description}@*
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Perform overflow checking on @var{relocation} which has
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@var{bitsize} significant bits and will be shifted right by
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@var{rightshift} bits, on a machine with addresses containing
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@var{addrsize} significant bits. The result is either of
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@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
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@findex bfd_perform_relocation
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@subsubsection @code{bfd_perform_relocation}
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@strong{Synopsis}
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@example
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bfd_reloc_status_type bfd_perform_relocation
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(bfd *abfd,
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arelent *reloc_entry,
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void *data,
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asection *input_section,
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bfd *output_bfd,
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char **error_message);
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@end example
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@strong{Description}@*
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If @var{output_bfd} is supplied to this function, the
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generated image will be relocatable; the relocations are
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copied to the output file after they have been changed to
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reflect the new state of the world. There are two ways of
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reflecting the results of partial linkage in an output file:
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by modifying the output data in place, and by modifying the
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relocation record. Some native formats (e.g., basic a.out and
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basic coff) have no way of specifying an addend in the
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relocation type, so the addend has to go in the output data.
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This is no big deal since in these formats the output data
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slot will always be big enough for the addend. Complex reloc
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types with addends were invented to solve just this problem.
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The @var{error_message} argument is set to an error message if
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this return @code{bfd_reloc_dangerous}.
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@findex bfd_install_relocation
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@subsubsection @code{bfd_install_relocation}
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@strong{Synopsis}
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@example
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bfd_reloc_status_type bfd_install_relocation
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(bfd *abfd,
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arelent *reloc_entry,
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void *data, bfd_vma data_start,
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asection *input_section,
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char **error_message);
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@end example
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@strong{Description}@*
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This looks remarkably like @code{bfd_perform_relocation}, except it
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does not expect that the section contents have been filled in.
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I.e., it's suitable for use when creating, rather than applying
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a relocation.
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For now, this function should be considered reserved for the
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assembler.
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@node howto manager, , typedef arelent, Relocations
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@section The howto manager
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When an application wants to create a relocation, but doesn't
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know what the target machine might call it, it can find out by
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using this bit of code.
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@findex bfd_reloc_code_type
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@subsubsection @code{bfd_reloc_code_type}
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@strong{Description}@*
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The insides of a reloc code. The idea is that, eventually, there
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will be one enumerator for every type of relocation we ever do.
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Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll
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return a howto pointer.
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This does mean that the application must determine the correct
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enumerator value; you can't get a howto pointer from a random set
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of attributes.
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Here are the possible values for @code{enum bfd_reloc_code_real}:
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@deffn {} BFD_RELOC_64
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@deffnx {} BFD_RELOC_32
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@deffnx {} BFD_RELOC_26
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@deffnx {} BFD_RELOC_24
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@deffnx {} BFD_RELOC_16
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@deffnx {} BFD_RELOC_14
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@deffnx {} BFD_RELOC_8
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Basic absolute relocations of N bits.
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@end deffn
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@deffn {} BFD_RELOC_64_PCREL
|
|
@deffnx {} BFD_RELOC_32_PCREL
|
|
@deffnx {} BFD_RELOC_24_PCREL
|
|
@deffnx {} BFD_RELOC_16_PCREL
|
|
@deffnx {} BFD_RELOC_12_PCREL
|
|
@deffnx {} BFD_RELOC_8_PCREL
|
|
PC-relative relocations. Sometimes these are relative to the address
|
|
of the relocation itself; sometimes they are relative to the start of
|
|
the section containing the relocation. It depends on the specific target.
|
|
|
|
The 24-bit relocation is used in some Intel 960 configurations.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_32_GOT_PCREL
|
|
@deffnx {} BFD_RELOC_16_GOT_PCREL
|
|
@deffnx {} BFD_RELOC_8_GOT_PCREL
|
|
@deffnx {} BFD_RELOC_32_GOTOFF
|
|
@deffnx {} BFD_RELOC_16_GOTOFF
|
|
@deffnx {} BFD_RELOC_LO16_GOTOFF
|
|
@deffnx {} BFD_RELOC_HI16_GOTOFF
|
|
@deffnx {} BFD_RELOC_HI16_S_GOTOFF
|
|
@deffnx {} BFD_RELOC_8_GOTOFF
|
|
@deffnx {} BFD_RELOC_64_PLT_PCREL
|
|
@deffnx {} BFD_RELOC_32_PLT_PCREL
|
|
@deffnx {} BFD_RELOC_24_PLT_PCREL
|
|
@deffnx {} BFD_RELOC_16_PLT_PCREL
|
|
@deffnx {} BFD_RELOC_8_PLT_PCREL
|
|
@deffnx {} BFD_RELOC_64_PLTOFF
|
|
@deffnx {} BFD_RELOC_32_PLTOFF
|
|
@deffnx {} BFD_RELOC_16_PLTOFF
|
|
@deffnx {} BFD_RELOC_LO16_PLTOFF
|
|
@deffnx {} BFD_RELOC_HI16_PLTOFF
|
|
@deffnx {} BFD_RELOC_HI16_S_PLTOFF
|
|
@deffnx {} BFD_RELOC_8_PLTOFF
|
|
For ELF.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_68K_GLOB_DAT
|
|
@deffnx {} BFD_RELOC_68K_JMP_SLOT
|
|
@deffnx {} BFD_RELOC_68K_RELATIVE
|
|
Relocations used by 68K ELF.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_32_BASEREL
|
|
@deffnx {} BFD_RELOC_16_BASEREL
|
|
@deffnx {} BFD_RELOC_LO16_BASEREL
|
|
@deffnx {} BFD_RELOC_HI16_BASEREL
|
|
@deffnx {} BFD_RELOC_HI16_S_BASEREL
|
|
@deffnx {} BFD_RELOC_8_BASEREL
|
|
@deffnx {} BFD_RELOC_RVA
|
|
Linkage-table relative.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_8_FFnn
|
|
Absolute 8-bit relocation, but used to form an address like 0xFFnn.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_32_PCREL_S2
|
|
@deffnx {} BFD_RELOC_16_PCREL_S2
|
|
@deffnx {} BFD_RELOC_23_PCREL_S2
|
|
These PC-relative relocations are stored as word displacements --
|
|
i.e., byte displacements shifted right two bits. The 30-bit word
|
|
displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
|
|
SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
|
|
signed 16-bit displacement is used on the MIPS, and the 23-bit
|
|
displacement is used on the Alpha.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_HI22
|
|
@deffnx {} BFD_RELOC_LO10
|
|
High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
|
|
the target word. These are used on the SPARC.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_GPREL16
|
|
@deffnx {} BFD_RELOC_GPREL32
|
|
For systems that allocate a Global Pointer register, these are
|
|
displacements off that register. These relocation types are
|
|
handled specially, because the value the register will have is
|
|
decided relatively late.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_I960_CALLJ
|
|
Reloc types used for i960/b.out.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_NONE
|
|
@deffnx {} BFD_RELOC_SPARC_WDISP22
|
|
@deffnx {} BFD_RELOC_SPARC22
|
|
@deffnx {} BFD_RELOC_SPARC13
|
|
@deffnx {} BFD_RELOC_SPARC_GOT10
|
|
@deffnx {} BFD_RELOC_SPARC_GOT13
|
|
@deffnx {} BFD_RELOC_SPARC_GOT22
|
|
@deffnx {} BFD_RELOC_SPARC_PC10
|
|
@deffnx {} BFD_RELOC_SPARC_PC22
|
|
@deffnx {} BFD_RELOC_SPARC_WPLT30
|
|
@deffnx {} BFD_RELOC_SPARC_COPY
|
|
@deffnx {} BFD_RELOC_SPARC_GLOB_DAT
|
|
@deffnx {} BFD_RELOC_SPARC_JMP_SLOT
|
|
@deffnx {} BFD_RELOC_SPARC_RELATIVE
|
|
@deffnx {} BFD_RELOC_SPARC_UA16
|
|
@deffnx {} BFD_RELOC_SPARC_UA32
|
|
@deffnx {} BFD_RELOC_SPARC_UA64
|
|
SPARC ELF relocations. There is probably some overlap with other
|
|
relocation types already defined.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_SPARC_BASE13
|
|
@deffnx {} BFD_RELOC_SPARC_BASE22
|
|
I think these are specific to SPARC a.out (e.g., Sun 4).
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_SPARC_64
|
|
@deffnx {} BFD_RELOC_SPARC_10
|
|
@deffnx {} BFD_RELOC_SPARC_11
|
|
@deffnx {} BFD_RELOC_SPARC_OLO10
|
|
@deffnx {} BFD_RELOC_SPARC_HH22
|
|
@deffnx {} BFD_RELOC_SPARC_HM10
|
|
@deffnx {} BFD_RELOC_SPARC_LM22
|
|
@deffnx {} BFD_RELOC_SPARC_PC_HH22
|
|
@deffnx {} BFD_RELOC_SPARC_PC_HM10
|
|
@deffnx {} BFD_RELOC_SPARC_PC_LM22
|
|
@deffnx {} BFD_RELOC_SPARC_WDISP16
|
|
@deffnx {} BFD_RELOC_SPARC_WDISP19
|
|
@deffnx {} BFD_RELOC_SPARC_7
|
|
@deffnx {} BFD_RELOC_SPARC_6
|
|
@deffnx {} BFD_RELOC_SPARC_5
|
|
@deffnx {} BFD_RELOC_SPARC_DISP64
|
|
@deffnx {} BFD_RELOC_SPARC_PLT32
|
|
@deffnx {} BFD_RELOC_SPARC_PLT64
|
|
@deffnx {} BFD_RELOC_SPARC_HIX22
|
|
@deffnx {} BFD_RELOC_SPARC_LOX10
|
|
@deffnx {} BFD_RELOC_SPARC_H44
|
|
@deffnx {} BFD_RELOC_SPARC_M44
|
|
@deffnx {} BFD_RELOC_SPARC_L44
|
|
@deffnx {} BFD_RELOC_SPARC_REGISTER
|
|
SPARC64 relocations
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_SPARC_REV32
|
|
SPARC little endian relocation
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32
|
|
@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64
|
|
SPARC TLS relocations
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16
|
|
Alpha ECOFF and ELF relocations. Some of these treat the symbol or
|
|
"addend" in some special way.
|
|
For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
|
|
writing; when reading, it will be the absolute section symbol. The
|
|
addend is the displacement in bytes of the "lda" instruction from
|
|
the "ldah" instruction (which is at the address of this reloc).
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16
|
|
For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
|
|
with GPDISP_HI16 relocs. The addend is ignored when writing the
|
|
relocations out, and is filled in with the file's GP value on
|
|
reading, for convenience.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_ALPHA_GPDISP
|
|
The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
|
|
relocation except that there is no accompanying GPDISP_LO16
|
|
relocation.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_ALPHA_LITERAL
|
|
@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL
|
|
@deffnx {} BFD_RELOC_ALPHA_LITUSE
|
|
The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
|
|
the assembler turns it into a LDQ instruction to load the address of
|
|
the symbol, and then fills in a register in the real instruction.
|
|
|
|
The LITERAL reloc, at the LDQ instruction, refers to the .lita
|
|
section symbol. The addend is ignored when writing, but is filled
|
|
in with the file's GP value on reading, for convenience, as with the
|
|
GPDISP_LO16 reloc.
|
|
|
|
The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
|
|
It should refer to the symbol to be referenced, as with 16_GOTOFF,
|
|
but it generates output not based on the position within the .got
|
|
section, but relative to the GP value chosen for the file during the
|
|
final link stage.
|
|
|
|
The LITUSE reloc, on the instruction using the loaded address, gives
|
|
information to the linker that it might be able to use to optimize
|
|
away some literal section references. The symbol is ignored (read
|
|
as the absolute section symbol), and the "addend" indicates the type
|
|
of instruction using the register:
|
|
1 - "memory" fmt insn
|
|
2 - byte-manipulation (byte offset reg)
|
|
3 - jsr (target of branch)
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_ALPHA_HINT
|
|
The HINT relocation indicates a value that should be filled into the
|
|
"hint" field of a jmp/jsr/ret instruction, for possible branch-
|
|
prediction logic which may be provided on some processors.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_ALPHA_LINKAGE
|
|
The LINKAGE relocation outputs a linkage pair in the object file,
|
|
which is filled by the linker.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_ALPHA_CODEADDR
|
|
The CODEADDR relocation outputs a STO_CA in the object file,
|
|
which is filled by the linker.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_ALPHA_GPREL_HI16
|
|
@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16
|
|
The GPREL_HI/LO relocations together form a 32-bit offset from the
|
|
GP register.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_ALPHA_BRSGP
|
|
Like BFD_RELOC_23_PCREL_S2, except that the source and target must
|
|
share a common GP, and the target address is adjusted for
|
|
STO_ALPHA_STD_GPLOAD.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_ALPHA_TLSGD
|
|
@deffnx {} BFD_RELOC_ALPHA_TLSLDM
|
|
@deffnx {} BFD_RELOC_ALPHA_DTPMOD64
|
|
@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16
|
|
@deffnx {} BFD_RELOC_ALPHA_DTPREL64
|
|
@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16
|
|
@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16
|
|
@deffnx {} BFD_RELOC_ALPHA_DTPREL16
|
|
@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16
|
|
@deffnx {} BFD_RELOC_ALPHA_TPREL64
|
|
@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16
|
|
@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16
|
|
@deffnx {} BFD_RELOC_ALPHA_TPREL16
|
|
Alpha thread-local storage relocations.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MIPS_JMP
|
|
Bits 27..2 of the relocation address shifted right 2 bits;
|
|
simple reloc otherwise.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MIPS16_JMP
|
|
The MIPS16 jump instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MIPS16_GPREL
|
|
MIPS16 GP relative reloc.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_HI16
|
|
High 16 bits of 32-bit value; simple reloc.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_HI16_S
|
|
High 16 bits of 32-bit value but the low 16 bits will be sign
|
|
extended and added to form the final result. If the low 16
|
|
bits form a negative number, we need to add one to the high value
|
|
to compensate for the borrow when the low bits are added.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_LO16
|
|
Low 16 bits.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_PCREL_HI16_S
|
|
Like BFD_RELOC_HI16_S, but PC relative.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_PCREL_LO16
|
|
Like BFD_RELOC_LO16, but PC relative.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MIPS_LITERAL
|
|
Relocation against a MIPS literal section.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MIPS_GOT16
|
|
@deffnx {} BFD_RELOC_MIPS_CALL16
|
|
@deffnx {} BFD_RELOC_MIPS_GOT_HI16
|
|
@deffnx {} BFD_RELOC_MIPS_GOT_LO16
|
|
@deffnx {} BFD_RELOC_MIPS_CALL_HI16
|
|
@deffnx {} BFD_RELOC_MIPS_CALL_LO16
|
|
@deffnx {} BFD_RELOC_MIPS_SUB
|
|
@deffnx {} BFD_RELOC_MIPS_GOT_PAGE
|
|
@deffnx {} BFD_RELOC_MIPS_GOT_OFST
|
|
@deffnx {} BFD_RELOC_MIPS_GOT_DISP
|
|
@deffnx {} BFD_RELOC_MIPS_SHIFT5
|
|
@deffnx {} BFD_RELOC_MIPS_SHIFT6
|
|
@deffnx {} BFD_RELOC_MIPS_INSERT_A
|
|
@deffnx {} BFD_RELOC_MIPS_INSERT_B
|
|
@deffnx {} BFD_RELOC_MIPS_DELETE
|
|
@deffnx {} BFD_RELOC_MIPS_HIGHEST
|
|
@deffnx {} BFD_RELOC_MIPS_HIGHER
|
|
@deffnx {} BFD_RELOC_MIPS_SCN_DISP
|
|
@deffnx {} BFD_RELOC_MIPS_REL16
|
|
@deffnx {} BFD_RELOC_MIPS_RELGOT
|
|
@deffnx {} BFD_RELOC_MIPS_JALR
|
|
MIPS ELF relocations.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_FRV_LABEL16
|
|
@deffnx {} BFD_RELOC_FRV_LABEL24
|
|
@deffnx {} BFD_RELOC_FRV_LO16
|
|
@deffnx {} BFD_RELOC_FRV_HI16
|
|
@deffnx {} BFD_RELOC_FRV_GPREL12
|
|
@deffnx {} BFD_RELOC_FRV_GPRELU12
|
|
@deffnx {} BFD_RELOC_FRV_GPREL32
|
|
@deffnx {} BFD_RELOC_FRV_GPRELHI
|
|
@deffnx {} BFD_RELOC_FRV_GPRELLO
|
|
@deffnx {} BFD_RELOC_FRV_GOT12
|
|
@deffnx {} BFD_RELOC_FRV_GOTHI
|
|
@deffnx {} BFD_RELOC_FRV_GOTLO
|
|
@deffnx {} BFD_RELOC_FRV_FUNCDESC
|
|
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12
|
|
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI
|
|
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO
|
|
@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE
|
|
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12
|
|
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
|
|
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
|
|
@deffnx {} BFD_RELOC_FRV_GOTOFF12
|
|
@deffnx {} BFD_RELOC_FRV_GOTOFFHI
|
|
@deffnx {} BFD_RELOC_FRV_GOTOFFLO
|
|
Fujitsu Frv Relocations.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MN10300_GOTOFF24
|
|
This is a 24bit GOT-relative reloc for the mn10300.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MN10300_GOT32
|
|
This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
|
|
in the instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MN10300_GOT24
|
|
This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
|
|
in the instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MN10300_GOT16
|
|
This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
|
|
in the instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MN10300_COPY
|
|
Copy symbol at runtime.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MN10300_GLOB_DAT
|
|
Create GOT entry.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MN10300_JMP_SLOT
|
|
Create PLT entry.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MN10300_RELATIVE
|
|
Adjust by program base.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_386_GOT32
|
|
@deffnx {} BFD_RELOC_386_PLT32
|
|
@deffnx {} BFD_RELOC_386_COPY
|
|
@deffnx {} BFD_RELOC_386_GLOB_DAT
|
|
@deffnx {} BFD_RELOC_386_JUMP_SLOT
|
|
@deffnx {} BFD_RELOC_386_RELATIVE
|
|
@deffnx {} BFD_RELOC_386_GOTOFF
|
|
@deffnx {} BFD_RELOC_386_GOTPC
|
|
@deffnx {} BFD_RELOC_386_TLS_TPOFF
|
|
@deffnx {} BFD_RELOC_386_TLS_IE
|
|
@deffnx {} BFD_RELOC_386_TLS_GOTIE
|
|
@deffnx {} BFD_RELOC_386_TLS_LE
|
|
@deffnx {} BFD_RELOC_386_TLS_GD
|
|
@deffnx {} BFD_RELOC_386_TLS_LDM
|
|
@deffnx {} BFD_RELOC_386_TLS_LDO_32
|
|
@deffnx {} BFD_RELOC_386_TLS_IE_32
|
|
@deffnx {} BFD_RELOC_386_TLS_LE_32
|
|
@deffnx {} BFD_RELOC_386_TLS_DTPMOD32
|
|
@deffnx {} BFD_RELOC_386_TLS_DTPOFF32
|
|
@deffnx {} BFD_RELOC_386_TLS_TPOFF32
|
|
i386/elf relocations
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_X86_64_GOT32
|
|
@deffnx {} BFD_RELOC_X86_64_PLT32
|
|
@deffnx {} BFD_RELOC_X86_64_COPY
|
|
@deffnx {} BFD_RELOC_X86_64_GLOB_DAT
|
|
@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT
|
|
@deffnx {} BFD_RELOC_X86_64_RELATIVE
|
|
@deffnx {} BFD_RELOC_X86_64_GOTPCREL
|
|
@deffnx {} BFD_RELOC_X86_64_32S
|
|
@deffnx {} BFD_RELOC_X86_64_DTPMOD64
|
|
@deffnx {} BFD_RELOC_X86_64_DTPOFF64
|
|
@deffnx {} BFD_RELOC_X86_64_TPOFF64
|
|
@deffnx {} BFD_RELOC_X86_64_TLSGD
|
|
@deffnx {} BFD_RELOC_X86_64_TLSLD
|
|
@deffnx {} BFD_RELOC_X86_64_DTPOFF32
|
|
@deffnx {} BFD_RELOC_X86_64_GOTTPOFF
|
|
@deffnx {} BFD_RELOC_X86_64_TPOFF32
|
|
x86-64/elf relocations
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_NS32K_IMM_8
|
|
@deffnx {} BFD_RELOC_NS32K_IMM_16
|
|
@deffnx {} BFD_RELOC_NS32K_IMM_32
|
|
@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL
|
|
@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL
|
|
@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL
|
|
@deffnx {} BFD_RELOC_NS32K_DISP_8
|
|
@deffnx {} BFD_RELOC_NS32K_DISP_16
|
|
@deffnx {} BFD_RELOC_NS32K_DISP_32
|
|
@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL
|
|
@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL
|
|
@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL
|
|
ns32k relocations
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL
|
|
@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL
|
|
PDP11 relocations
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_PJ_CODE_HI16
|
|
@deffnx {} BFD_RELOC_PJ_CODE_LO16
|
|
@deffnx {} BFD_RELOC_PJ_CODE_DIR16
|
|
@deffnx {} BFD_RELOC_PJ_CODE_DIR32
|
|
@deffnx {} BFD_RELOC_PJ_CODE_REL16
|
|
@deffnx {} BFD_RELOC_PJ_CODE_REL32
|
|
Picojava relocs. Not all of these appear in object files.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_PPC_B26
|
|
@deffnx {} BFD_RELOC_PPC_BA26
|
|
@deffnx {} BFD_RELOC_PPC_TOC16
|
|
@deffnx {} BFD_RELOC_PPC_B16
|
|
@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN
|
|
@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN
|
|
@deffnx {} BFD_RELOC_PPC_BA16
|
|
@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN
|
|
@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN
|
|
@deffnx {} BFD_RELOC_PPC_COPY
|
|
@deffnx {} BFD_RELOC_PPC_GLOB_DAT
|
|
@deffnx {} BFD_RELOC_PPC_JMP_SLOT
|
|
@deffnx {} BFD_RELOC_PPC_RELATIVE
|
|
@deffnx {} BFD_RELOC_PPC_LOCAL24PC
|
|
@deffnx {} BFD_RELOC_PPC_EMB_NADDR32
|
|
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16
|
|
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO
|
|
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI
|
|
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA
|
|
@deffnx {} BFD_RELOC_PPC_EMB_SDAI16
|
|
@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16
|
|
@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL
|
|
@deffnx {} BFD_RELOC_PPC_EMB_SDA21
|
|
@deffnx {} BFD_RELOC_PPC_EMB_MRKREF
|
|
@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16
|
|
@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO
|
|
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI
|
|
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA
|
|
@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD
|
|
@deffnx {} BFD_RELOC_PPC_EMB_RELSDA
|
|
@deffnx {} BFD_RELOC_PPC64_HIGHER
|
|
@deffnx {} BFD_RELOC_PPC64_HIGHER_S
|
|
@deffnx {} BFD_RELOC_PPC64_HIGHEST
|
|
@deffnx {} BFD_RELOC_PPC64_HIGHEST_S
|
|
@deffnx {} BFD_RELOC_PPC64_TOC16_LO
|
|
@deffnx {} BFD_RELOC_PPC64_TOC16_HI
|
|
@deffnx {} BFD_RELOC_PPC64_TOC16_HA
|
|
@deffnx {} BFD_RELOC_PPC64_TOC
|
|
@deffnx {} BFD_RELOC_PPC64_PLTGOT16
|
|
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO
|
|
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI
|
|
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA
|
|
@deffnx {} BFD_RELOC_PPC64_ADDR16_DS
|
|
@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS
|
|
@deffnx {} BFD_RELOC_PPC64_GOT16_DS
|
|
@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS
|
|
@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS
|
|
@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS
|
|
@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS
|
|
@deffnx {} BFD_RELOC_PPC64_TOC16_DS
|
|
@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS
|
|
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS
|
|
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS
|
|
Power(rs6000) and PowerPC relocations.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_PPC_TLS
|
|
@deffnx {} BFD_RELOC_PPC_DTPMOD
|
|
@deffnx {} BFD_RELOC_PPC_TPREL16
|
|
@deffnx {} BFD_RELOC_PPC_TPREL16_LO
|
|
@deffnx {} BFD_RELOC_PPC_TPREL16_HI
|
|
@deffnx {} BFD_RELOC_PPC_TPREL16_HA
|
|
@deffnx {} BFD_RELOC_PPC_TPREL
|
|
@deffnx {} BFD_RELOC_PPC_DTPREL16
|
|
@deffnx {} BFD_RELOC_PPC_DTPREL16_LO
|
|
@deffnx {} BFD_RELOC_PPC_DTPREL16_HI
|
|
@deffnx {} BFD_RELOC_PPC_DTPREL16_HA
|
|
@deffnx {} BFD_RELOC_PPC_DTPREL
|
|
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16
|
|
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO
|
|
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI
|
|
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA
|
|
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16
|
|
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO
|
|
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI
|
|
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA
|
|
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16
|
|
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO
|
|
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI
|
|
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA
|
|
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16
|
|
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO
|
|
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI
|
|
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA
|
|
@deffnx {} BFD_RELOC_PPC64_TPREL16_DS
|
|
@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS
|
|
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER
|
|
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA
|
|
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST
|
|
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA
|
|
@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS
|
|
@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS
|
|
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER
|
|
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA
|
|
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST
|
|
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA
|
|
PowerPC and PowerPC64 thread-local storage relocations.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_I370_D12
|
|
IBM 370/390 relocations
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_CTOR
|
|
The type of reloc used to build a constructor table - at the moment
|
|
probably a 32 bit wide absolute relocation, but the target can choose.
|
|
It generally does map to one of the other relocation types.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_ARM_PCREL_BRANCH
|
|
ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
|
|
not stored in the instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_ARM_PCREL_BLX
|
|
ARM 26 bit pc-relative branch. The lowest bit must be zero and is
|
|
not stored in the instruction. The 2nd lowest bit comes from a 1 bit
|
|
field in the instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_THUMB_PCREL_BLX
|
|
Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
|
|
not stored in the instruction. The 2nd lowest bit comes from a 1 bit
|
|
field in the instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_ARM_IMMEDIATE
|
|
@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE
|
|
@deffnx {} BFD_RELOC_ARM_OFFSET_IMM
|
|
@deffnx {} BFD_RELOC_ARM_SHIFT_IMM
|
|
@deffnx {} BFD_RELOC_ARM_SWI
|
|
@deffnx {} BFD_RELOC_ARM_MULTI
|
|
@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM
|
|
@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2
|
|
@deffnx {} BFD_RELOC_ARM_ADR_IMM
|
|
@deffnx {} BFD_RELOC_ARM_LDR_IMM
|
|
@deffnx {} BFD_RELOC_ARM_LITERAL
|
|
@deffnx {} BFD_RELOC_ARM_IN_POOL
|
|
@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8
|
|
@deffnx {} BFD_RELOC_ARM_HWLITERAL
|
|
@deffnx {} BFD_RELOC_ARM_THUMB_ADD
|
|
@deffnx {} BFD_RELOC_ARM_THUMB_IMM
|
|
@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT
|
|
@deffnx {} BFD_RELOC_ARM_THUMB_OFFSET
|
|
@deffnx {} BFD_RELOC_ARM_GOT12
|
|
@deffnx {} BFD_RELOC_ARM_GOT32
|
|
@deffnx {} BFD_RELOC_ARM_JUMP_SLOT
|
|
@deffnx {} BFD_RELOC_ARM_COPY
|
|
@deffnx {} BFD_RELOC_ARM_GLOB_DAT
|
|
@deffnx {} BFD_RELOC_ARM_PLT32
|
|
@deffnx {} BFD_RELOC_ARM_RELATIVE
|
|
@deffnx {} BFD_RELOC_ARM_GOTOFF
|
|
@deffnx {} BFD_RELOC_ARM_GOTPC
|
|
These relocs are only used within the ARM assembler. They are not
|
|
(at present) written to any object files.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_SH_PCDISP8BY2
|
|
@deffnx {} BFD_RELOC_SH_PCDISP12BY2
|
|
@deffnx {} BFD_RELOC_SH_IMM4
|
|
@deffnx {} BFD_RELOC_SH_IMM4BY2
|
|
@deffnx {} BFD_RELOC_SH_IMM4BY4
|
|
@deffnx {} BFD_RELOC_SH_IMM8
|
|
@deffnx {} BFD_RELOC_SH_IMM8BY2
|
|
@deffnx {} BFD_RELOC_SH_IMM8BY4
|
|
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2
|
|
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4
|
|
@deffnx {} BFD_RELOC_SH_SWITCH16
|
|
@deffnx {} BFD_RELOC_SH_SWITCH32
|
|
@deffnx {} BFD_RELOC_SH_USES
|
|
@deffnx {} BFD_RELOC_SH_COUNT
|
|
@deffnx {} BFD_RELOC_SH_ALIGN
|
|
@deffnx {} BFD_RELOC_SH_CODE
|
|
@deffnx {} BFD_RELOC_SH_DATA
|
|
@deffnx {} BFD_RELOC_SH_LABEL
|
|
@deffnx {} BFD_RELOC_SH_LOOP_START
|
|
@deffnx {} BFD_RELOC_SH_LOOP_END
|
|
@deffnx {} BFD_RELOC_SH_COPY
|
|
@deffnx {} BFD_RELOC_SH_GLOB_DAT
|
|
@deffnx {} BFD_RELOC_SH_JMP_SLOT
|
|
@deffnx {} BFD_RELOC_SH_RELATIVE
|
|
@deffnx {} BFD_RELOC_SH_GOTPC
|
|
@deffnx {} BFD_RELOC_SH_GOT_LOW16
|
|
@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16
|
|
@deffnx {} BFD_RELOC_SH_GOT_MEDHI16
|
|
@deffnx {} BFD_RELOC_SH_GOT_HI16
|
|
@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16
|
|
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16
|
|
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16
|
|
@deffnx {} BFD_RELOC_SH_GOTPLT_HI16
|
|
@deffnx {} BFD_RELOC_SH_PLT_LOW16
|
|
@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16
|
|
@deffnx {} BFD_RELOC_SH_PLT_MEDHI16
|
|
@deffnx {} BFD_RELOC_SH_PLT_HI16
|
|
@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16
|
|
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16
|
|
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16
|
|
@deffnx {} BFD_RELOC_SH_GOTOFF_HI16
|
|
@deffnx {} BFD_RELOC_SH_GOTPC_LOW16
|
|
@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16
|
|
@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16
|
|
@deffnx {} BFD_RELOC_SH_GOTPC_HI16
|
|
@deffnx {} BFD_RELOC_SH_COPY64
|
|
@deffnx {} BFD_RELOC_SH_GLOB_DAT64
|
|
@deffnx {} BFD_RELOC_SH_JMP_SLOT64
|
|
@deffnx {} BFD_RELOC_SH_RELATIVE64
|
|
@deffnx {} BFD_RELOC_SH_GOT10BY4
|
|
@deffnx {} BFD_RELOC_SH_GOT10BY8
|
|
@deffnx {} BFD_RELOC_SH_GOTPLT10BY4
|
|
@deffnx {} BFD_RELOC_SH_GOTPLT10BY8
|
|
@deffnx {} BFD_RELOC_SH_GOTPLT32
|
|
@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE
|
|
@deffnx {} BFD_RELOC_SH_IMMU5
|
|
@deffnx {} BFD_RELOC_SH_IMMS6
|
|
@deffnx {} BFD_RELOC_SH_IMMS6BY32
|
|
@deffnx {} BFD_RELOC_SH_IMMU6
|
|
@deffnx {} BFD_RELOC_SH_IMMS10
|
|
@deffnx {} BFD_RELOC_SH_IMMS10BY2
|
|
@deffnx {} BFD_RELOC_SH_IMMS10BY4
|
|
@deffnx {} BFD_RELOC_SH_IMMS10BY8
|
|
@deffnx {} BFD_RELOC_SH_IMMS16
|
|
@deffnx {} BFD_RELOC_SH_IMMU16
|
|
@deffnx {} BFD_RELOC_SH_IMM_LOW16
|
|
@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL
|
|
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16
|
|
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL
|
|
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16
|
|
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL
|
|
@deffnx {} BFD_RELOC_SH_IMM_HI16
|
|
@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL
|
|
@deffnx {} BFD_RELOC_SH_PT_16
|
|
@deffnx {} BFD_RELOC_SH_TLS_GD_32
|
|
@deffnx {} BFD_RELOC_SH_TLS_LD_32
|
|
@deffnx {} BFD_RELOC_SH_TLS_LDO_32
|
|
@deffnx {} BFD_RELOC_SH_TLS_IE_32
|
|
@deffnx {} BFD_RELOC_SH_TLS_LE_32
|
|
@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32
|
|
@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32
|
|
@deffnx {} BFD_RELOC_SH_TLS_TPOFF32
|
|
Renesas / SuperH SH relocs. Not all of these appear in object files.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH9
|
|
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12
|
|
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23
|
|
Thumb 23-, 12- and 9-bit pc-relative branches. The lowest bit must
|
|
be zero and is not stored in the instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_ARC_B22_PCREL
|
|
ARC Cores relocs.
|
|
ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
|
|
not stored in the instruction. The high 20 bits are installed in bits 26
|
|
through 7 of the instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_ARC_B26
|
|
ARC 26 bit absolute branch. The lowest two bits must be zero and are not
|
|
stored in the instruction. The high 24 bits are installed in bits 23
|
|
through 0.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_D10V_10_PCREL_R
|
|
Mitsubishi D10V relocs.
|
|
This is a 10-bit reloc with the right 2 bits
|
|
assumed to be 0.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_D10V_10_PCREL_L
|
|
Mitsubishi D10V relocs.
|
|
This is a 10-bit reloc with the right 2 bits
|
|
assumed to be 0. This is the same as the previous reloc
|
|
except it is in the left container, i.e.,
|
|
shifted left 15 bits.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_D10V_18
|
|
This is an 18-bit reloc with the right 2 bits
|
|
assumed to be 0.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_D10V_18_PCREL
|
|
This is an 18-bit reloc with the right 2 bits
|
|
assumed to be 0.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_D30V_6
|
|
Mitsubishi D30V relocs.
|
|
This is a 6-bit absolute reloc.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_D30V_9_PCREL
|
|
This is a 6-bit pc-relative reloc with
|
|
the right 3 bits assumed to be 0.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_D30V_9_PCREL_R
|
|
This is a 6-bit pc-relative reloc with
|
|
the right 3 bits assumed to be 0. Same
|
|
as the previous reloc but on the right side
|
|
of the container.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_D30V_15
|
|
This is a 12-bit absolute reloc with the
|
|
right 3 bitsassumed to be 0.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_D30V_15_PCREL
|
|
This is a 12-bit pc-relative reloc with
|
|
the right 3 bits assumed to be 0.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_D30V_15_PCREL_R
|
|
This is a 12-bit pc-relative reloc with
|
|
the right 3 bits assumed to be 0. Same
|
|
as the previous reloc but on the right side
|
|
of the container.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_D30V_21
|
|
This is an 18-bit absolute reloc with
|
|
the right 3 bits assumed to be 0.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_D30V_21_PCREL
|
|
This is an 18-bit pc-relative reloc with
|
|
the right 3 bits assumed to be 0.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_D30V_21_PCREL_R
|
|
This is an 18-bit pc-relative reloc with
|
|
the right 3 bits assumed to be 0. Same
|
|
as the previous reloc but on the right side
|
|
of the container.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_D30V_32
|
|
This is a 32-bit absolute reloc.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_D30V_32_PCREL
|
|
This is a 32-bit pc-relative reloc.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_DLX_HI16_S
|
|
DLX relocs
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_DLX_LO16
|
|
DLX relocs
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_DLX_JMP26
|
|
DLX relocs
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M32R_24
|
|
Renesas M32R (formerly Mitsubishi M32R) relocs.
|
|
This is a 24 bit absolute address.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M32R_10_PCREL
|
|
This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M32R_18_PCREL
|
|
This is an 18-bit reloc with the right 2 bits assumed to be 0.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M32R_26_PCREL
|
|
This is a 26-bit reloc with the right 2 bits assumed to be 0.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M32R_HI16_ULO
|
|
This is a 16-bit reloc containing the high 16 bits of an address
|
|
used when the lower 16 bits are treated as unsigned.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M32R_HI16_SLO
|
|
This is a 16-bit reloc containing the high 16 bits of an address
|
|
used when the lower 16 bits are treated as signed.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M32R_LO16
|
|
This is a 16-bit reloc containing the lower 16 bits of an address.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M32R_SDA16
|
|
This is a 16-bit reloc containing the small data area offset for use in
|
|
add3, load, and store instructions.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M32R_GOT24
|
|
@deffnx {} BFD_RELOC_M32R_26_PLTREL
|
|
@deffnx {} BFD_RELOC_M32R_COPY
|
|
@deffnx {} BFD_RELOC_M32R_GLOB_DAT
|
|
@deffnx {} BFD_RELOC_M32R_JMP_SLOT
|
|
@deffnx {} BFD_RELOC_M32R_RELATIVE
|
|
@deffnx {} BFD_RELOC_M32R_GOTOFF
|
|
@deffnx {} BFD_RELOC_M32R_GOTPC24
|
|
@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO
|
|
@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO
|
|
@deffnx {} BFD_RELOC_M32R_GOT16_LO
|
|
@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO
|
|
@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO
|
|
@deffnx {} BFD_RELOC_M32R_GOTPC_LO
|
|
For PIC.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_9_PCREL
|
|
This is a 9-bit reloc
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_22_PCREL
|
|
This is a 22-bit reloc
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET
|
|
This is a 16 bit offset from the short data area pointer.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET
|
|
This is a 16 bit offset (of which only 15 bits are used) from the
|
|
short data area pointer.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET
|
|
This is a 16 bit offset from the zero data area pointer.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET
|
|
This is a 16 bit offset (of which only 15 bits are used) from the
|
|
zero data area pointer.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET
|
|
This is an 8 bit offset (of which only 6 bits are used) from the
|
|
tiny data area pointer.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET
|
|
This is an 8bit offset (of which only 7 bits are used) from the tiny
|
|
data area pointer.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET
|
|
This is a 7 bit offset from the tiny data area pointer.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET
|
|
This is a 16 bit offset from the tiny data area pointer.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET
|
|
This is a 5 bit offset (of which only 4 bits are used) from the tiny
|
|
data area pointer.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET
|
|
This is a 4 bit offset from the tiny data area pointer.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
|
|
This is a 16 bit offset from the short data area pointer, with the
|
|
bits placed non-contiguously in the instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
|
|
This is a 16 bit offset from the zero data area pointer, with the
|
|
bits placed non-contiguously in the instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET
|
|
This is a 6 bit offset from the call table base pointer.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET
|
|
This is a 16 bit offset from the call table base pointer.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_LONGCALL
|
|
Used for relaxing indirect function calls.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_LONGJUMP
|
|
Used for relaxing indirect jumps.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_V850_ALIGN
|
|
Used to maintain alignment whilst relaxing.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MN10300_32_PCREL
|
|
This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
|
|
instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MN10300_16_PCREL
|
|
This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
|
|
instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_TIC30_LDP
|
|
This is a 8bit DP reloc for the tms320c30, where the most
|
|
significant 8 bits of a 24 bit word are placed into the least
|
|
significant 8 bits of the opcode.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_TIC54X_PARTLS7
|
|
This is a 7bit reloc for the tms320c54x, where the least
|
|
significant 7 bits of a 16 bit word are placed into the least
|
|
significant 7 bits of the opcode.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_TIC54X_PARTMS9
|
|
This is a 9bit DP reloc for the tms320c54x, where the most
|
|
significant 9 bits of a 16 bit word are placed into the least
|
|
significant 9 bits of the opcode.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_TIC54X_23
|
|
This is an extended address 23-bit reloc for the tms320c54x.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_TIC54X_16_OF_23
|
|
This is a 16-bit reloc for the tms320c54x, where the least
|
|
significant 16 bits of a 23-bit extended address are placed into
|
|
the opcode.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_TIC54X_MS7_OF_23
|
|
This is a reloc for the tms320c54x, where the most
|
|
significant 7 bits of a 23-bit extended address are placed into
|
|
the opcode.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_FR30_48
|
|
This is a 48 bit reloc for the FR30 that stores 32 bits.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_FR30_20
|
|
This is a 32 bit reloc for the FR30 that stores 20 bits split up into
|
|
two sections.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_FR30_6_IN_4
|
|
This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
|
|
4 bits.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_FR30_8_IN_8
|
|
This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
|
|
into 8 bits.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_FR30_9_IN_8
|
|
This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
|
|
into 8 bits.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_FR30_10_IN_8
|
|
This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
|
|
into 8 bits.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_FR30_9_PCREL
|
|
This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
|
|
short offset into 8 bits.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_FR30_12_PCREL
|
|
This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
|
|
short offset into 11 bits.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4
|
|
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2
|
|
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2
|
|
@deffnx {} BFD_RELOC_MCORE_PCREL_32
|
|
@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
|
|
@deffnx {} BFD_RELOC_MCORE_RVA
|
|
Motorola Mcore relocations.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MMIX_GETA
|
|
@deffnx {} BFD_RELOC_MMIX_GETA_1
|
|
@deffnx {} BFD_RELOC_MMIX_GETA_2
|
|
@deffnx {} BFD_RELOC_MMIX_GETA_3
|
|
These are relocations for the GETA instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MMIX_CBRANCH
|
|
@deffnx {} BFD_RELOC_MMIX_CBRANCH_J
|
|
@deffnx {} BFD_RELOC_MMIX_CBRANCH_1
|
|
@deffnx {} BFD_RELOC_MMIX_CBRANCH_2
|
|
@deffnx {} BFD_RELOC_MMIX_CBRANCH_3
|
|
These are relocations for a conditional branch instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MMIX_PUSHJ
|
|
@deffnx {} BFD_RELOC_MMIX_PUSHJ_1
|
|
@deffnx {} BFD_RELOC_MMIX_PUSHJ_2
|
|
@deffnx {} BFD_RELOC_MMIX_PUSHJ_3
|
|
@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE
|
|
These are relocations for the PUSHJ instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MMIX_JMP
|
|
@deffnx {} BFD_RELOC_MMIX_JMP_1
|
|
@deffnx {} BFD_RELOC_MMIX_JMP_2
|
|
@deffnx {} BFD_RELOC_MMIX_JMP_3
|
|
These are relocations for the JMP instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MMIX_ADDR19
|
|
This is a relocation for a relative address as in a GETA instruction or
|
|
a branch.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MMIX_ADDR27
|
|
This is a relocation for a relative address as in a JMP instruction.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE
|
|
This is a relocation for an instruction field that may be a general
|
|
register or a value 0..255.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MMIX_REG
|
|
This is a relocation for an instruction field that may be a general
|
|
register.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET
|
|
This is a relocation for two instruction fields holding a register and
|
|
an offset, the equivalent of the relocation.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MMIX_LOCAL
|
|
This relocation is an assertion that the expression is not allocated as
|
|
a global register. It does not modify contents.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_7_PCREL
|
|
This is a 16 bit reloc for the AVR that stores 8 bit pc relative
|
|
short offset into 7 bits.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_13_PCREL
|
|
This is a 16 bit reloc for the AVR that stores 13 bit pc relative
|
|
short offset into 12 bits.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_16_PM
|
|
This is a 16 bit reloc for the AVR that stores 17 bit value (usually
|
|
program memory address) into 16 bits.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_LO8_LDI
|
|
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
|
|
data memory address) into 8 bit immediate value of LDI insn.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_HI8_LDI
|
|
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
|
|
of data memory address) into 8 bit immediate value of LDI insn.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_HH8_LDI
|
|
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
|
|
of program memory address) into 8 bit immediate value of LDI insn.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG
|
|
This is a 16 bit reloc for the AVR that stores negated 8 bit value
|
|
(usually data memory address) into 8 bit immediate value of SUBI insn.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG
|
|
This is a 16 bit reloc for the AVR that stores negated 8 bit value
|
|
(high 8 bit of data memory address) into 8 bit immediate value of
|
|
SUBI insn.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG
|
|
This is a 16 bit reloc for the AVR that stores negated 8 bit value
|
|
(most high 8 bit of program memory address) into 8 bit immediate value
|
|
of LDI or SUBI insn.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM
|
|
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
|
|
command address) into 8 bit immediate value of LDI insn.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM
|
|
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
|
|
of command address) into 8 bit immediate value of LDI insn.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM
|
|
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
|
|
of command address) into 8 bit immediate value of LDI insn.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG
|
|
This is a 16 bit reloc for the AVR that stores negated 8 bit value
|
|
(usually command address) into 8 bit immediate value of SUBI insn.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG
|
|
This is a 16 bit reloc for the AVR that stores negated 8 bit value
|
|
(high 8 bit of 16 bit command address) into 8 bit immediate value
|
|
of SUBI insn.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG
|
|
This is a 16 bit reloc for the AVR that stores negated 8 bit value
|
|
(high 6 bit of 22 bit command address) into 8 bit immediate
|
|
value of SUBI insn.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_AVR_CALL
|
|
This is a 32 bit reloc for the AVR that stores 23 bit value
|
|
into 22 bits.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_12
|
|
Direct 12 bit.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_GOT12
|
|
12 bit GOT offset.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_PLT32
|
|
32 bit PC relative PLT address.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_COPY
|
|
Copy symbol at runtime.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_GLOB_DAT
|
|
Create GOT entry.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_JMP_SLOT
|
|
Create PLT entry.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_RELATIVE
|
|
Adjust by program base.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_GOTPC
|
|
32 bit PC relative offset to GOT.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_GOT16
|
|
16 bit GOT offset.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_PC16DBL
|
|
PC relative 16 bit shifted by 1.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_PLT16DBL
|
|
16 bit PC rel. PLT shifted by 1.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_PC32DBL
|
|
PC relative 32 bit shifted by 1.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_PLT32DBL
|
|
32 bit PC rel. PLT shifted by 1.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_GOTPCDBL
|
|
32 bit PC rel. GOT shifted by 1.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_GOT64
|
|
64 bit GOT offset.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_PLT64
|
|
64 bit PC relative PLT address.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_GOTENT
|
|
32 bit rel. offset to GOT entry.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_GOTOFF64
|
|
64 bit offset to GOT.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_GOTPLT12
|
|
12-bit offset to symbol-entry within GOT, with PLT handling.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_GOTPLT16
|
|
16-bit offset to symbol-entry within GOT, with PLT handling.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_GOTPLT32
|
|
32-bit offset to symbol-entry within GOT, with PLT handling.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_GOTPLT64
|
|
64-bit offset to symbol-entry within GOT, with PLT handling.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_GOTPLTENT
|
|
32-bit rel. offset to symbol-entry within GOT, with PLT handling.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_PLTOFF16
|
|
16-bit rel. offset from the GOT to a PLT entry.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_PLTOFF32
|
|
32-bit rel. offset from the GOT to a PLT entry.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_PLTOFF64
|
|
64-bit rel. offset from the GOT to a PLT entry.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_TLS_LOAD
|
|
@deffnx {} BFD_RELOC_390_TLS_GDCALL
|
|
@deffnx {} BFD_RELOC_390_TLS_LDCALL
|
|
@deffnx {} BFD_RELOC_390_TLS_GD32
|
|
@deffnx {} BFD_RELOC_390_TLS_GD64
|
|
@deffnx {} BFD_RELOC_390_TLS_GOTIE12
|
|
@deffnx {} BFD_RELOC_390_TLS_GOTIE32
|
|
@deffnx {} BFD_RELOC_390_TLS_GOTIE64
|
|
@deffnx {} BFD_RELOC_390_TLS_LDM32
|
|
@deffnx {} BFD_RELOC_390_TLS_LDM64
|
|
@deffnx {} BFD_RELOC_390_TLS_IE32
|
|
@deffnx {} BFD_RELOC_390_TLS_IE64
|
|
@deffnx {} BFD_RELOC_390_TLS_IEENT
|
|
@deffnx {} BFD_RELOC_390_TLS_LE32
|
|
@deffnx {} BFD_RELOC_390_TLS_LE64
|
|
@deffnx {} BFD_RELOC_390_TLS_LDO32
|
|
@deffnx {} BFD_RELOC_390_TLS_LDO64
|
|
@deffnx {} BFD_RELOC_390_TLS_DTPMOD
|
|
@deffnx {} BFD_RELOC_390_TLS_DTPOFF
|
|
@deffnx {} BFD_RELOC_390_TLS_TPOFF
|
|
s390 tls relocations.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_390_20
|
|
@deffnx {} BFD_RELOC_390_GOT20
|
|
@deffnx {} BFD_RELOC_390_GOTPLT20
|
|
@deffnx {} BFD_RELOC_390_TLS_GOTIE20
|
|
Long displacement extension.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_IP2K_FR9
|
|
Scenix IP2K - 9-bit register number / data address
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_IP2K_BANK
|
|
Scenix IP2K - 4-bit register/data bank number
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_IP2K_ADDR16CJP
|
|
Scenix IP2K - low 13 bits of instruction word address
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_IP2K_PAGE3
|
|
Scenix IP2K - high 3 bits of instruction word address
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_IP2K_LO8DATA
|
|
@deffnx {} BFD_RELOC_IP2K_HI8DATA
|
|
@deffnx {} BFD_RELOC_IP2K_EX8DATA
|
|
Scenix IP2K - ext/low/high 8 bits of data address
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_IP2K_LO8INSN
|
|
@deffnx {} BFD_RELOC_IP2K_HI8INSN
|
|
Scenix IP2K - low/high 8 bits of instruction word address
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_IP2K_PC_SKIP
|
|
Scenix IP2K - even/odd PC modifier to modify snb pcl.0
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_IP2K_TEXT
|
|
Scenix IP2K - 16 bit word address in text section.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_IP2K_FR_OFFSET
|
|
Scenix IP2K - 7-bit sp or dp offset
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_VPE4KMATH_DATA
|
|
@deffnx {} BFD_RELOC_VPE4KMATH_INSN
|
|
Scenix VPE4K coprocessor - data/insn-space addressing
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_VTABLE_INHERIT
|
|
@deffnx {} BFD_RELOC_VTABLE_ENTRY
|
|
These two relocations are used by the linker to determine which of
|
|
the entries in a C++ virtual function table are actually used. When
|
|
the --gc-sections option is given, the linker will zero out the entries
|
|
that are not used, so that the code for those functions need not be
|
|
included in the output.
|
|
|
|
VTABLE_INHERIT is a zero-space relocation used to describe to the
|
|
linker the inheritance tree of a C++ virtual function table. The
|
|
relocation's symbol should be the parent class' vtable, and the
|
|
relocation should be located at the child vtable.
|
|
|
|
VTABLE_ENTRY is a zero-space relocation that describes the use of a
|
|
virtual function table entry. The reloc's symbol should refer to the
|
|
table of the class mentioned in the code. Off of that base, an offset
|
|
describes the entry that is being used. For Rela hosts, this offset
|
|
is stored in the reloc's addend. For Rel hosts, we are forced to put
|
|
this offset in the reloc's section offset.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_IA64_IMM14
|
|
@deffnx {} BFD_RELOC_IA64_IMM22
|
|
@deffnx {} BFD_RELOC_IA64_IMM64
|
|
@deffnx {} BFD_RELOC_IA64_DIR32MSB
|
|
@deffnx {} BFD_RELOC_IA64_DIR32LSB
|
|
@deffnx {} BFD_RELOC_IA64_DIR64MSB
|
|
@deffnx {} BFD_RELOC_IA64_DIR64LSB
|
|
@deffnx {} BFD_RELOC_IA64_GPREL22
|
|
@deffnx {} BFD_RELOC_IA64_GPREL64I
|
|
@deffnx {} BFD_RELOC_IA64_GPREL32MSB
|
|
@deffnx {} BFD_RELOC_IA64_GPREL32LSB
|
|
@deffnx {} BFD_RELOC_IA64_GPREL64MSB
|
|
@deffnx {} BFD_RELOC_IA64_GPREL64LSB
|
|
@deffnx {} BFD_RELOC_IA64_LTOFF22
|
|
@deffnx {} BFD_RELOC_IA64_LTOFF64I
|
|
@deffnx {} BFD_RELOC_IA64_PLTOFF22
|
|
@deffnx {} BFD_RELOC_IA64_PLTOFF64I
|
|
@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB
|
|
@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB
|
|
@deffnx {} BFD_RELOC_IA64_FPTR64I
|
|
@deffnx {} BFD_RELOC_IA64_FPTR32MSB
|
|
@deffnx {} BFD_RELOC_IA64_FPTR32LSB
|
|
@deffnx {} BFD_RELOC_IA64_FPTR64MSB
|
|
@deffnx {} BFD_RELOC_IA64_FPTR64LSB
|
|
@deffnx {} BFD_RELOC_IA64_PCREL21B
|
|
@deffnx {} BFD_RELOC_IA64_PCREL21BI
|
|
@deffnx {} BFD_RELOC_IA64_PCREL21M
|
|
@deffnx {} BFD_RELOC_IA64_PCREL21F
|
|
@deffnx {} BFD_RELOC_IA64_PCREL22
|
|
@deffnx {} BFD_RELOC_IA64_PCREL60B
|
|
@deffnx {} BFD_RELOC_IA64_PCREL64I
|
|
@deffnx {} BFD_RELOC_IA64_PCREL32MSB
|
|
@deffnx {} BFD_RELOC_IA64_PCREL32LSB
|
|
@deffnx {} BFD_RELOC_IA64_PCREL64MSB
|
|
@deffnx {} BFD_RELOC_IA64_PCREL64LSB
|
|
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22
|
|
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I
|
|
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB
|
|
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB
|
|
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB
|
|
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB
|
|
@deffnx {} BFD_RELOC_IA64_SEGREL32MSB
|
|
@deffnx {} BFD_RELOC_IA64_SEGREL32LSB
|
|
@deffnx {} BFD_RELOC_IA64_SEGREL64MSB
|
|
@deffnx {} BFD_RELOC_IA64_SEGREL64LSB
|
|
@deffnx {} BFD_RELOC_IA64_SECREL32MSB
|
|
@deffnx {} BFD_RELOC_IA64_SECREL32LSB
|
|
@deffnx {} BFD_RELOC_IA64_SECREL64MSB
|
|
@deffnx {} BFD_RELOC_IA64_SECREL64LSB
|
|
@deffnx {} BFD_RELOC_IA64_REL32MSB
|
|
@deffnx {} BFD_RELOC_IA64_REL32LSB
|
|
@deffnx {} BFD_RELOC_IA64_REL64MSB
|
|
@deffnx {} BFD_RELOC_IA64_REL64LSB
|
|
@deffnx {} BFD_RELOC_IA64_LTV32MSB
|
|
@deffnx {} BFD_RELOC_IA64_LTV32LSB
|
|
@deffnx {} BFD_RELOC_IA64_LTV64MSB
|
|
@deffnx {} BFD_RELOC_IA64_LTV64LSB
|
|
@deffnx {} BFD_RELOC_IA64_IPLTMSB
|
|
@deffnx {} BFD_RELOC_IA64_IPLTLSB
|
|
@deffnx {} BFD_RELOC_IA64_COPY
|
|
@deffnx {} BFD_RELOC_IA64_LTOFF22X
|
|
@deffnx {} BFD_RELOC_IA64_LDXMOV
|
|
@deffnx {} BFD_RELOC_IA64_TPREL14
|
|
@deffnx {} BFD_RELOC_IA64_TPREL22
|
|
@deffnx {} BFD_RELOC_IA64_TPREL64I
|
|
@deffnx {} BFD_RELOC_IA64_TPREL64MSB
|
|
@deffnx {} BFD_RELOC_IA64_TPREL64LSB
|
|
@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22
|
|
@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB
|
|
@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB
|
|
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22
|
|
@deffnx {} BFD_RELOC_IA64_DTPREL14
|
|
@deffnx {} BFD_RELOC_IA64_DTPREL22
|
|
@deffnx {} BFD_RELOC_IA64_DTPREL64I
|
|
@deffnx {} BFD_RELOC_IA64_DTPREL32MSB
|
|
@deffnx {} BFD_RELOC_IA64_DTPREL32LSB
|
|
@deffnx {} BFD_RELOC_IA64_DTPREL64MSB
|
|
@deffnx {} BFD_RELOC_IA64_DTPREL64LSB
|
|
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22
|
|
Intel IA64 Relocations.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M68HC11_HI8
|
|
Motorola 68HC11 reloc.
|
|
This is the 8 bit high part of an absolute address.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M68HC11_LO8
|
|
Motorola 68HC11 reloc.
|
|
This is the 8 bit low part of an absolute address.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M68HC11_3B
|
|
Motorola 68HC11 reloc.
|
|
This is the 3 bit of a value.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M68HC11_RL_JUMP
|
|
Motorola 68HC11 reloc.
|
|
This reloc marks the beginning of a jump/call instruction.
|
|
It is used for linker relaxation to correctly identify beginning
|
|
of instruction and change some branches to use PC-relative
|
|
addressing mode.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M68HC11_RL_GROUP
|
|
Motorola 68HC11 reloc.
|
|
This reloc marks a group of several instructions that gcc generates
|
|
and for which the linker relaxation pass can modify and/or remove
|
|
some of them.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M68HC11_LO16
|
|
Motorola 68HC11 reloc.
|
|
This is the 16-bit lower part of an address. It is used for 'call'
|
|
instruction to specify the symbol address without any special
|
|
transformation (due to memory bank window).
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M68HC11_PAGE
|
|
Motorola 68HC11 reloc.
|
|
This is a 8-bit reloc that specifies the page number of an address.
|
|
It is used by 'call' instruction to specify the page number of
|
|
the symbol.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M68HC11_24
|
|
Motorola 68HC11 reloc.
|
|
This is a 24-bit reloc that represents the address with a 16-bit
|
|
value and a 8-bit page number. The symbol address is transformed
|
|
to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_M68HC12_5B
|
|
Motorola 68HC12 reloc.
|
|
This is the 5 bits of a value.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_CRIS_BDISP8
|
|
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5
|
|
@deffnx {} BFD_RELOC_CRIS_SIGNED_6
|
|
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6
|
|
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4
|
|
These relocs are only used within the CRIS assembler. They are not
|
|
(at present) written to any object files.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_CRIS_COPY
|
|
@deffnx {} BFD_RELOC_CRIS_GLOB_DAT
|
|
@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT
|
|
@deffnx {} BFD_RELOC_CRIS_RELATIVE
|
|
Relocs used in ELF shared libraries for CRIS.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_CRIS_32_GOT
|
|
32-bit offset to symbol-entry within GOT.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_CRIS_16_GOT
|
|
16-bit offset to symbol-entry within GOT.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_CRIS_32_GOTPLT
|
|
32-bit offset to symbol-entry within GOT, with PLT handling.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_CRIS_16_GOTPLT
|
|
16-bit offset to symbol-entry within GOT, with PLT handling.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_CRIS_32_GOTREL
|
|
32-bit offset to symbol, relative to GOT.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL
|
|
32-bit offset to symbol with PLT entry, relative to GOT.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL
|
|
32-bit offset to symbol with PLT entry, relative to this relocation.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_860_COPY
|
|
@deffnx {} BFD_RELOC_860_GLOB_DAT
|
|
@deffnx {} BFD_RELOC_860_JUMP_SLOT
|
|
@deffnx {} BFD_RELOC_860_RELATIVE
|
|
@deffnx {} BFD_RELOC_860_PC26
|
|
@deffnx {} BFD_RELOC_860_PLT26
|
|
@deffnx {} BFD_RELOC_860_PC16
|
|
@deffnx {} BFD_RELOC_860_LOW0
|
|
@deffnx {} BFD_RELOC_860_SPLIT0
|
|
@deffnx {} BFD_RELOC_860_LOW1
|
|
@deffnx {} BFD_RELOC_860_SPLIT1
|
|
@deffnx {} BFD_RELOC_860_LOW2
|
|
@deffnx {} BFD_RELOC_860_SPLIT2
|
|
@deffnx {} BFD_RELOC_860_LOW3
|
|
@deffnx {} BFD_RELOC_860_LOGOT0
|
|
@deffnx {} BFD_RELOC_860_SPGOT0
|
|
@deffnx {} BFD_RELOC_860_LOGOT1
|
|
@deffnx {} BFD_RELOC_860_SPGOT1
|
|
@deffnx {} BFD_RELOC_860_LOGOTOFF0
|
|
@deffnx {} BFD_RELOC_860_SPGOTOFF0
|
|
@deffnx {} BFD_RELOC_860_LOGOTOFF1
|
|
@deffnx {} BFD_RELOC_860_SPGOTOFF1
|
|
@deffnx {} BFD_RELOC_860_LOGOTOFF2
|
|
@deffnx {} BFD_RELOC_860_LOGOTOFF3
|
|
@deffnx {} BFD_RELOC_860_LOPC
|
|
@deffnx {} BFD_RELOC_860_HIGHADJ
|
|
@deffnx {} BFD_RELOC_860_HAGOT
|
|
@deffnx {} BFD_RELOC_860_HAGOTOFF
|
|
@deffnx {} BFD_RELOC_860_HAPC
|
|
@deffnx {} BFD_RELOC_860_HIGH
|
|
@deffnx {} BFD_RELOC_860_HIGOT
|
|
@deffnx {} BFD_RELOC_860_HIGOTOFF
|
|
Intel i860 Relocations.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_OPENRISC_ABS_26
|
|
@deffnx {} BFD_RELOC_OPENRISC_REL_26
|
|
OpenRISC Relocations.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_H8_DIR16A8
|
|
@deffnx {} BFD_RELOC_H8_DIR16R8
|
|
@deffnx {} BFD_RELOC_H8_DIR24A8
|
|
@deffnx {} BFD_RELOC_H8_DIR24R8
|
|
@deffnx {} BFD_RELOC_H8_DIR32A16
|
|
H8 elf Relocations.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_XSTORMY16_REL_12
|
|
@deffnx {} BFD_RELOC_XSTORMY16_12
|
|
@deffnx {} BFD_RELOC_XSTORMY16_24
|
|
@deffnx {} BFD_RELOC_XSTORMY16_FPTR16
|
|
Sony Xstormy16 Relocations.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_VAX_GLOB_DAT
|
|
@deffnx {} BFD_RELOC_VAX_JMP_SLOT
|
|
@deffnx {} BFD_RELOC_VAX_RELATIVE
|
|
Relocations used by VAX ELF.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_MSP430_10_PCREL
|
|
@deffnx {} BFD_RELOC_MSP430_16_PCREL
|
|
@deffnx {} BFD_RELOC_MSP430_16
|
|
@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE
|
|
@deffnx {} BFD_RELOC_MSP430_16_BYTE
|
|
msp430 specific relocation codes
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_IQ2000_OFFSET_16
|
|
@deffnx {} BFD_RELOC_IQ2000_OFFSET_21
|
|
@deffnx {} BFD_RELOC_IQ2000_UHI16
|
|
IQ2000 Relocations.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_XTENSA_RTLD
|
|
Special Xtensa relocation used only by PLT entries in ELF shared
|
|
objects to indicate that the runtime linker should set the value
|
|
to one of its own internal functions or data structures.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_XTENSA_GLOB_DAT
|
|
@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT
|
|
@deffnx {} BFD_RELOC_XTENSA_RELATIVE
|
|
Xtensa relocations for ELF shared objects.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_XTENSA_PLT
|
|
Xtensa relocation used in ELF object files for symbols that may require
|
|
PLT entries. Otherwise, this is just a generic 32-bit relocation.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_XTENSA_OP0
|
|
@deffnx {} BFD_RELOC_XTENSA_OP1
|
|
@deffnx {} BFD_RELOC_XTENSA_OP2
|
|
Generic Xtensa relocations. Only the operand number is encoded
|
|
in the relocation. The details are determined by extracting the
|
|
instruction opcode.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND
|
|
Xtensa relocation to mark that the assembler expanded the
|
|
instructions from an original target. The expansion size is
|
|
encoded in the reloc size.
|
|
@end deffn
|
|
@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY
|
|
Xtensa relocation to mark that the linker should simplify
|
|
assembler-expanded instructions. This is commonly used
|
|
internally by the linker after analysis of a
|
|
BFD_RELOC_XTENSA_ASM_EXPAND.
|
|
@end deffn
|
|
|
|
@example
|
|
|
|
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
|
|
@end example
|
|
@findex bfd_reloc_type_lookup
|
|
@subsubsection @code{bfd_reloc_type_lookup}
|
|
@strong{Synopsis}
|
|
@example
|
|
reloc_howto_type *bfd_reloc_type_lookup
|
|
(bfd *abfd, bfd_reloc_code_real_type code);
|
|
@end example
|
|
@strong{Description}@*
|
|
Return a pointer to a howto structure which, when
|
|
invoked, will perform the relocation @var{code} on data from the
|
|
architecture noted.
|
|
|
|
@findex bfd_default_reloc_type_lookup
|
|
@subsubsection @code{bfd_default_reloc_type_lookup}
|
|
@strong{Synopsis}
|
|
@example
|
|
reloc_howto_type *bfd_default_reloc_type_lookup
|
|
(bfd *abfd, bfd_reloc_code_real_type code);
|
|
@end example
|
|
@strong{Description}@*
|
|
Provides a default relocation lookup routine for any architecture.
|
|
|
|
@findex bfd_get_reloc_code_name
|
|
@subsubsection @code{bfd_get_reloc_code_name}
|
|
@strong{Synopsis}
|
|
@example
|
|
const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
|
|
@end example
|
|
@strong{Description}@*
|
|
Provides a printable name for the supplied relocation code.
|
|
Useful mainly for printing error messages.
|
|
|
|
@findex bfd_generic_relax_section
|
|
@subsubsection @code{bfd_generic_relax_section}
|
|
@strong{Synopsis}
|
|
@example
|
|
bfd_boolean bfd_generic_relax_section
|
|
(bfd *abfd,
|
|
asection *section,
|
|
struct bfd_link_info *,
|
|
bfd_boolean *);
|
|
@end example
|
|
@strong{Description}@*
|
|
Provides default handling for relaxing for back ends which
|
|
don't do relaxing -- i.e., does nothing except make sure that the
|
|
final size of the section is set.
|
|
|
|
@findex bfd_generic_gc_sections
|
|
@subsubsection @code{bfd_generic_gc_sections}
|
|
@strong{Synopsis}
|
|
@example
|
|
bfd_boolean bfd_generic_gc_sections
|
|
(bfd *, struct bfd_link_info *);
|
|
@end example
|
|
@strong{Description}@*
|
|
Provides default handling for relaxing for back ends which
|
|
don't do section gc -- i.e., does nothing.
|
|
|
|
@findex bfd_generic_merge_sections
|
|
@subsubsection @code{bfd_generic_merge_sections}
|
|
@strong{Synopsis}
|
|
@example
|
|
bfd_boolean bfd_generic_merge_sections
|
|
(bfd *, struct bfd_link_info *);
|
|
@end example
|
|
@strong{Description}@*
|
|
Provides default handling for SEC_MERGE section merging for back ends
|
|
which don't have SEC_MERGE support -- i.e., does nothing.
|
|
|
|
@findex bfd_generic_get_relocated_section_contents
|
|
@subsubsection @code{bfd_generic_get_relocated_section_contents}
|
|
@strong{Synopsis}
|
|
@example
|
|
bfd_byte *bfd_generic_get_relocated_section_contents
|
|
(bfd *abfd,
|
|
struct bfd_link_info *link_info,
|
|
struct bfd_link_order *link_order,
|
|
bfd_byte *data,
|
|
bfd_boolean relocatable,
|
|
asymbol **symbols);
|
|
@end example
|
|
@strong{Description}@*
|
|
Provides default handling of relocation effort for back ends
|
|
which can't be bothered to do it efficiently.
|
|
|