0d2a298904
- This is heavily derived from John Baldwin's apic/pci cleanup on i386. - I have completely rewritten or drastically cleaned up some other parts. (in particular, bootstrap) - This is still a WIP. It seems that there are some highly bogus bioses on nVidia nForce3-150 boards. I can't stress how broken these boards are. I have a workaround in mind, but right now the Asus SK8N is broken. The Gigabyte K8NPro (nVidia based) is also mind-numbingly hosed. - Most of my testing has been with SCHED_ULE. SCHED_4BSD works. - the apic and acpi components are 'standard'. - If you have an nVidia nForce3-150 board, you are stuck with 'device atpic' in addition, because they somehow managed to forget to connect the 8254 timer to the apic, even though its in the same silicon! ARGH! This directly violates the ACPI spec.
169 lines
5.3 KiB
C
169 lines
5.3 KiB
C
/*-
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* Copyright (c) Peter Wemm <peter@netplex.com.au>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PCPU_H_
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#define _MACHINE_PCPU_H_
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#ifdef _KERNEL
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/*
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* The SMP parts are setup in pmap.c and locore.s for the BSP, and
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* mp_machdep.c sets up the data for the AP's to "see" when they awake.
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* The reason for doing it via a struct is so that an array of pointers
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* to each CPU's data can be set up for things like "check curproc on all
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* other processors"
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*/
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#define PCPU_MD_FIELDS \
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struct pcpu *pc_prvspace; /* Self-reference */ \
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struct pmap *pc_curpmap; \
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struct amd64tss *pc_tssp; \
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register_t pc_rsp0; \
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register_t pc_scratch_rsp; /* User %rsp in syscall */ \
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u_int pc_apic_id; \
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u_int pc_acpi_id /* ACPI CPU id */
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#if defined(lint)
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extern struct pcpu *pcpup;
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#define PCPU_GET(member) (pcpup->pc_ ## member)
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#define PCPU_PTR(member) (&pcpup->pc_ ## member)
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#define PCPU_SET(member,value) (pcpup->pc_ ## member = (value))
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#elif defined(__GNUC__)
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/*
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* Evaluates to the byte offset of the per-cpu variable name.
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*/
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#define __pcpu_offset(name) \
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__offsetof(struct pcpu, name)
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/*
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* Evaluates to the type of the per-cpu variable name.
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*/
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#define __pcpu_type(name) \
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__typeof(((struct pcpu *)0)->name)
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/*
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* Evaluates to the address of the per-cpu variable name.
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*/
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#define __PCPU_PTR(name) __extension__ ({ \
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__pcpu_type(name) *__p; \
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\
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__asm __volatile("movq %%gs:%1,%0; addq %2,%0" \
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: "=r" (__p) \
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: "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace))), \
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"i" (__pcpu_offset(name))); \
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\
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__p; \
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})
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/*
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* Evaluates to the value of the per-cpu variable name.
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*/
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#define __PCPU_GET(name) __extension__ ({ \
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__pcpu_type(name) __result; \
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\
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if (sizeof(__result) == 1) { \
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u_char __b; \
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__asm __volatile("movb %%gs:%1,%0" \
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: "=r" (__b) \
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: "m" (*(u_char *)(__pcpu_offset(name)))); \
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__result = *(__pcpu_type(name) *)&__b; \
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} else if (sizeof(__result) == 2) { \
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u_short __w; \
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__asm __volatile("movw %%gs:%1,%0" \
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: "=r" (__w) \
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: "m" (*(u_short *)(__pcpu_offset(name)))); \
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__result = *(__pcpu_type(name) *)&__w; \
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} else if (sizeof(__result) == 4) { \
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u_int __i; \
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__asm __volatile("movl %%gs:%1,%0" \
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: "=r" (__i) \
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: "m" (*(u_int *)(__pcpu_offset(name)))); \
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__result = *(__pcpu_type(name) *)&__i; \
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} else if (sizeof(__result) == 8) { \
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u_long __l; \
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__asm __volatile("movq %%gs:%1,%0" \
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: "=r" (__l) \
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: "m" (*(u_long *)(__pcpu_offset(name)))); \
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__result = *(__pcpu_type(name) *)&__l; \
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} else { \
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__result = *__PCPU_PTR(name); \
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} \
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\
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__result; \
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})
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/*
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* Sets the value of the per-cpu variable name to value val.
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*/
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#define __PCPU_SET(name, val) { \
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__pcpu_type(name) __val = (val); \
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\
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if (sizeof(__val) == 1) { \
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u_char __b; \
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__b = *(u_char *)&__val; \
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__asm __volatile("movb %1,%%gs:%0" \
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: "=m" (*(u_char *)(__pcpu_offset(name))) \
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: "r" (__b)); \
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} else if (sizeof(__val) == 2) { \
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u_short __w; \
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__w = *(u_short *)&__val; \
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__asm __volatile("movw %1,%%gs:%0" \
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: "=m" (*(u_short *)(__pcpu_offset(name))) \
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: "r" (__w)); \
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} else if (sizeof(__val) == 4) { \
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u_int __i; \
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__i = *(u_int *)&__val; \
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__asm __volatile("movl %1,%%gs:%0" \
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: "=m" (*(u_int *)(__pcpu_offset(name))) \
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: "r" (__i)); \
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} else if (sizeof(__val) == 8) { \
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u_long __l; \
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__l = *(u_long *)&__val; \
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__asm __volatile("movq %1,%%gs:%0" \
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: "=m" (*(u_long *)(__pcpu_offset(name))) \
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: "r" (__l)); \
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} else { \
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*__PCPU_PTR(name) = __val; \
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} \
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}
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#define PCPU_GET(member) __PCPU_GET(pc_ ## member)
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#define PCPU_PTR(member) __PCPU_PTR(pc_ ## member)
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#define PCPU_SET(member, val) __PCPU_SET(pc_ ## member, val)
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#else
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#error gcc or lint is required to use this file
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#endif
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#endif /* _KERNEL */
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#endif /* ! _MACHINE_PCPU_H_ */
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