f7a5c9d346
This is a MIPS4KC CPU with various embedded peripherals, including wireless and ethernet support. This commit includes the platform, UART, ethernet MAC and GPIO support. The interrupt-driven GPIO code is disabled for now pending GPIO changes from the submitter. Submitted by: Aleksandr Rybalko <ray@dlink.ua>
369 lines
12 KiB
C
369 lines
12 KiB
C
/*-
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* Copyright (c) 2010 Aleksandr Rybalko.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _RT305XREG_H_
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#define _RT305XREG_H_
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/* XXX: must move to config */
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#define RT305X 1
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#define RT305XF 1
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#define RT3052F 1
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#define __U_BOOT__ 1
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/* XXX: must move to config */
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#ifdef RT3052F
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#define PLATFORM_COUNTER_FREQ (384 * 1000 * 1000)
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#endif
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#ifdef RT3050F
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#define PLATFORM_COUNTER_FREQ (320 * 1000 * 1000)
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#endif
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#ifndef PLATFORM_COUNTER_FREQ
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#error "Nor RT3052F nor RT3050F defined"
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#endif
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#define SYSTEM_CLOCK (PLATFORM_COUNTER_FREQ/3)
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#define SDRAM_BASE 0x00000000
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#define SDRAM_END 0x03FFFFFF
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#define SYSCTL_BASE 0x10000000
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#define SYSCTL_END 0x100000FF
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#define TIMER_BASE 0x10000100
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#define TIMER_END 0x100001FF
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#define INTCTL_BASE 0x10000200
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#define INTCTL_END 0x100002FF
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#define MEMCTRL_BASE 0x10000300
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#define MEMCTRL_END 0x100003FF /* SDRAM & Flash/SRAM */
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#define PCM_BASE 0x10000400
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#define PCM_END 0x100004FF
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#define UART_BASE 0x10000500
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#define UART_END 0x100005FF
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#define PIO_BASE 0x10000600
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#define PIO_END 0x100006FF
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#define GDMA_BASE 0x10000700
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#define GDMA_END 0x100007FF /* Generic DMA */
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#define NANDFC_BASE 0x10000800
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#define NANDFC_END 0x100008FF /* NAND Flash Controller */
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#define I2C_BASE 0x10000900
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#define I2C_END 0x100009FF
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#define I2S_BASE 0x10000A00
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#define I2S_END 0x10000AFF
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#define SPI_BASE 0x10000B00
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#define SPI_END 0x10000BFF
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#define UARTLITE_BASE 0x10000C00
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#define UARTLITE_END 0x10000CFF
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#define FRENG_BASE 0x10100000
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#define FRENG_END 0x1010FFFF /* Frame Engine */
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#define ETHSW_BASE 0x10110000
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#define ETHSW_END 0x10117FFF /* Ethernet Switch */
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#define ROM_BASE 0x10118000
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#define ROM_END 0x10119FFF
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#define WLAN_BASE 0x10180000
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#define WLAN_END 0x101BFFFF /* 802.11n MAC/BBP */
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#define USB_OTG_BASE 0x101C0000
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#define USB_OTG_END 0x101FFFFF
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#define EMEM_BASE 0x1B000000
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#define EMEM_END 0x1BFFFFFF /* External SRAM/Flash */
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#define FLASH_BASE 0x1F000000
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#define FLASH_END 0x1FFFFFFF /* Flash window */
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#define OBIO_MEM_BASE SYSCTL_BASE
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#define OBIO_MEM_START OBIO_MEM_BASE
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#define OBIO_MEM_END FLASH_END
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/* System Control */
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#define SYSCTL_CHIPID0_3 0x00 /* 'R''T''3''0' */
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#define SYSCTL_CHIPID4_7 0x04 /* '5''2'' '' ' */
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#define SYSCTL_SYSCFG 0x10
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#define SYSCTL_SYSCFG_INIC_EE_SDRAM (1<<29)
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#define SYSCTL_SYSCFG_INIC_8MB_SDRAM (1<<28)
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#define SYSCTL_SYSCFG_GE0_MODE_MASK 0x03000000
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#define SYSCTL_SYSCFG_GE0_MODE_SHIFT 24
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#define SYSCTL_SYSCFG_GE0_MODE_RGMII 0 /* RGMII Mode */
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#define SYSCTL_SYSCFG_GE0_MODE_MII 1 /* MII Mode */
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#define SYSCTL_SYSCFG_GE0_MODE_REV_MII 2 /*Reversed MII Mode*/
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#define SYSCTL_SYSCFG_BOOT_ADDR_1F00 (1<<22)
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#define SYSCTL_SYSCFG_BYPASS_PLL (1<<21)
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#define SYSCTL_SYSCFG_BIG_ENDIAN (1<<20)
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#define SYSCTL_SYSCFG_CPU_CLK_SEL_384MHZ (1<<18)
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#define SYSCTL_SYSCFG_BOOT_FROM_MASK 0x00030000
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#define SYSCTL_SYSCFG_BOOT_FROM_SHIFT 16
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#define SYSCTL_SYSCFG_BOOT_FROM_FLASH16 0
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#define SYSCTL_SYSCFG_BOOT_FROM_FLASH8 1
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#define SYSCTL_SYSCFG_BOOT_FROM_NANDFLASH 2
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#define SYSCTL_SYSCFG_BOOT_FROM_ROM 3
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#define SYSCTL_SYSCFG_TEST_CODE_MASK 0x0000ff00
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#define SYSCTL_SYSCFG_TEST_CODE_SHIFT 8
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#define SYSCTL_SYSCFG_SRAM_CS_MODE_MASK 0x0000000c
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#define SYSCTL_SYSCFG_SRAM_CS_MODE_SHIFT 2
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#define SYSCTL_SYSCFG_SRAM_CS_MODE_SRAM 0
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#define SYSCTL_SYSCFG_SRAM_CS_MODE_WDOG_RST 1
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#define SYSCTL_SYSCFG_SRAM_CS_MODE_BT_COEX 2
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#define SYSCTL_SYSCFG_SDRAM_CLK_DRV (1<<0) /* 8mA/12mA */
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#define SYSCTL_TESTSTAT 0x18
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#define SYSCTL_TESTSTAT2 0x1C
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#define SYSCTL_CLKCFG0 0x2C
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#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_MASK 0xc0000000
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#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_SHIFT 30
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#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_ZERO_DELAY 0
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#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_1NS_DELAY 1
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#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_2NS_DELAY 2
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#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_3NS_DELAY 3
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#define SYSCTL_CLKCFG1 0x30
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#define SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2 (1<<30)
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#define SYSCTL_CLKCFG1_OTG_CLK_EN (1<<18)
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#define SYSCTL_CLKCFG1_I2S_CLK_EN (1<<15)
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#define SYSCTL_CLKCFG1_I2S_CLK_SEL_EXT (1<<14)
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#define SYSCTL_CLKCFG1_I2S_CLK_DIV_MASK 0x00003f00
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#define SYSCTL_CLKCFG1_I2S_CLK_DIV_SHIFT 8
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#define SYSCTL_CLKCFG1_PCM_CLK_EN (1<<7)
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#define SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT (1<<6)
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#define SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK 0x0000003f
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#define SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT 0
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#define SYSCTL_RSTCTRL 0x34
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#define SYSCTL_RSTCTRL_ETHSW (1<<23)
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#define SYSCTL_RSTCTRL_OTG (1<<22)
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#define SYSCTL_RSTCTRL_FRENG (1<<21)
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#define SYSCTL_RSTCTRL_WLAN (1<<20)
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#define SYSCTL_RSTCTRL_UARTL (1<<19)
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#define SYSCTL_RSTCTRL_SPI (1<<18)
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#define SYSCTL_RSTCTRL_I2S (1<<17)
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#define SYSCTL_RSTCTRL_I2C (1<<16)
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#define SYSCTL_RSTCTRL_DMA (1<<14)
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#define SYSCTL_RSTCTRL_PIO (1<<13)
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#define SYSCTL_RSTCTRL_UART (1<<12)
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#define SYSCTL_RSTCTRL_PCM (1<<11)
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#define SYSCTL_RSTCTRL_MC (1<<10)
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#define SYSCTL_RSTCTRL_INTC (1<<9)
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#define SYSCTL_RSTCTRL_TIMER (1<<8)
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#define SYSCTL_RSTCTRL_SYS (1<<0)
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#define SYSCTL_RSTSTAT 0x38
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#define SYSCTL_RSTSTAT_SWCPURST (1<<3)
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#define SYSCTL_RSTSTAT_SWSYSRST (1<<2)
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#define SYSCTL_RSTSTAT_WDRST (1<<1)
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#define SYSCTL_GPIOMODE 0x60
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#define SYSCTL_GPIOMODE_RGMII_GPIO_MODE (1<<9)
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#define SYSCTL_GPIOMODE_SDRAM_GPIO_MODE (1<<8)
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#define SYSCTL_GPIOMODE_MDIO_GPIO_MODE (1<<7)
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#define SYSCTL_GPIOMODE_JTAG_GPIO_MODE (1<<6)
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#define SYSCTL_GPIOMODE_UARTL_GPIO_MODE (1<<5)
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#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_UARTF (0<<2)
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#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_UARTF (1<<2)
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#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_I2S (2<<2)
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#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_I2S_UARTF (3<<2)
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#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_GPIO (4<<2)
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#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO_UARTF (5<<2)
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#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO_I2S (6<<2)
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#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO (7<<2)
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#define SYSCTL_GPIOMODE_SPI_GPIO_MODE (1<<1)
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#define SYSCTL_GPIOMODE_I2C_GPIO_MODE (1<<0)
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#define SYSCTL_MEMO0 0x68
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#define SYSCTL_MEMO1 0x6C
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/* Timer */
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#define TIMER_TMRSTAT 0x00
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#define TIMER_TMRSTAT_TMR1RST (1<<5)
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#define TIMER_TMRSTAT_TMR0RST (1<<4)
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#define TIMER_TMRSTAT_TMR1INT (1<<1)
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#define TIMER_TMRSTAT_TMR0INT (1<<0)
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#define TIMER_TMR0LOAD 0x10
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#define TIMER_TMR0VAL 0x14
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#define TIMER_TMR0CTL 0x18
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#define TIMER_TMR1LOAD 0x20
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#define TIMER_TMR1VAL 0x24
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#define TIMER_TMR1CTL 0x28
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#define TIMER_TMRLOAD_TMR0LOAD_MASK 0xffff
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#define TIMER_TMRVAL_TMR0VAL_MASK 0xffff
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#define TIMER_TMRCTL_ENABLE (1<<7)
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#define TIMER_TMRCTL_MODE_MASK 0x00000030
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#define TIMER_TMRCTL_MODE_SHIFT 4
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#define TIMER_TMRCTL_MODE_FREE 0
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#define TIMER_TMRCTL_MODE_PERIODIC 1
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#define TIMER_TMRCTL_MODE_TIMOUT 2
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#define TIMER_TMRCTL_MODE_TIMOUT3 3
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#define TIMER_TMRCTL_PRESCALE_MASK 0x0000000f
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#define TIMER_TMRCTL_PRESCALE_SHIFT 0
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#define TIMER_TMRCTL_PRESCALE_NONE 0
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#define TIMER_TMRCTL_PRESCALE_BY_4 1
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#define TIMER_TMRCTL_PRESCALE_BY_8 2
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#define TIMER_TMRCTL_PRESCALE_BY_16 3
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#define TIMER_TMRCTL_PRESCALE_BY_32 4
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#define TIMER_TMRCTL_PRESCALE_BY_64 5
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#define TIMER_TMRCTL_PRESCALE_BY_128 6
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#define TIMER_TMRCTL_PRESCALE_BY_256 7
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#define TIMER_TMRCTL_PRESCALE_BY_512 8
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#define TIMER_TMRCTL_PRESCALE_BY_1K 9
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#define TIMER_TMRCTL_PRESCALE_BY_2K 10
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#define TIMER_TMRCTL_PRESCALE_BY_4K 11
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#define TIMER_TMRCTL_PRESCALE_BY_8K 12
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#define TIMER_TMRCTL_PRESCALE_BY_16K 13
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#define TIMER_TMRCTL_PRESCALE_BY_32K 14
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#define TIMER_TMRCTL_PRESCALE_BY_64K 15
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/* Interrupt Controller */
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#define IC_IRQ0STAT 0x00
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#define IC_IRQ1STAT 0x04
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#define IC_INTTYPE 0x20
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#define IC_INTRAW 0x30
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#define IC_INT_ENA 0x34
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#define IC_INT_DIS 0x38
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#define IC_OTG 18
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#define IC_ETHSW 17
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#define IC_UARTLITE 12
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#define IC_I2S 10
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#define IC_PERFC 9
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#define IC_NAND 8
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#define IC_DMA 7
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#define IC_PIO 6
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#define IC_UART 5
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#define IC_PCM 4
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#define IC_ILL_ACCESS 3
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#define IC_WDTIMER 2
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#define IC_TIMER0 1
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#define IC_SYSCTL 0
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#define IC_LINE_GLOBAL (1<<31) /* Only for DIS/ENA regs */
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#define IC_LINE_OTG (1<<18)
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#define IC_LINE_ETHSW (1<<17)
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#define IC_LINE_UARTLITE (1<<12)
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#define IC_LINE_I2S (1<<10)
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#define IC_LINE_PERFC (1<<9)
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#define IC_LINE_NAND (1<<8)
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#define IC_LINE_DMA (1<<7)
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#define IC_LINE_PIO (1<<6)
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#define IC_LINE_UART (1<<5)
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#define IC_LINE_PCM (1<<4)
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#define IC_LINE_ILL_ACCESS (1<<3)
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#define IC_LINE_WDTIMER (1<<2)
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#define IC_LINE_TIMER0 (1<<1)
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#define IC_LINE_SYSCTL (1<<0)
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#define IC_INT_MASK 0x000617ff
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/* GPIO */
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#define GPIO23_00_INT 0x00 /* Programmed I/O Int Status */
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#define GPIO23_00_EDGE 0x04 /* Programmed I/O Edge Status */
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#define GPIO23_00_RENA 0x08 /* Programmed I/O Int on Rising */
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#define GPIO23_00_FENA 0x0C /* Programmed I/O Int on Falling */
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#define GPIO23_00_DATA 0x20 /* Programmed I/O Data */
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#define GPIO23_00_DIR 0x24 /* Programmed I/O Direction */
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#define GPIO23_00_POL 0x28 /* Programmed I/O Pin Polarity */
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#define GPIO23_00_SET 0x2C /* Set PIO Data Bit */
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#define GPIO23_00_RESET 0x30 /* Clear PIO Data bit */
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#define GPIO23_00_TOG 0x34 /* Toggle PIO Data bit */
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#define GPIO39_24_INT 0x38
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#define GPIO39_24_EDGE 0x3c
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#define GPIO39_24_RENA 0x40
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#define GPIO39_24_FENA 0x44
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#define GPIO39_24_DATA 0x48
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#define GPIO39_24_DIR 0x4c
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#define GPIO39_24_POL 0x50
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#define GPIO39_24_SET 0x54
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#define GPIO39_24_RESET 0x58
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#define GPIO39_24_TOG 0x5c
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#define GPIO51_40_INT 0x60
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#define GPIO51_40_EDGE 0x64
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#define GPIO51_40_RENA 0x68
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#define GPIO51_40_FENA 0x6C
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#define GPIO51_40_DATA 0x70
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#define GPIO51_40_DIR 0x74
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#define GPIO51_40_POL 0x78
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#define GPIO51_40_SET 0x7C
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#define GPIO51_40_RESET 0x80
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#define GPIO51_40_TOG 0x84
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#define GDMA_CHANNEL_REQ0 0
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#define GDMA_CHANNEL_REQ1 1 /* (NAND-flash) */
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#define GDMA_CHANNEL_REQ2 2 /* (I2S) */
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#define GDMA_CHANNEL_REQ3 3 /* (PCM0-RX) */
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#define GDMA_CHANNEL_REQ4 4 /* (PCM1-RX) */
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#define GDMA_CHANNEL_REQ5 5 /* (PCM0-TX) */
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#define GDMA_CHANNEL_REQ6 6 /* (PCM1-TX) */
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#define GDMA_CHANNEL_REQ7 7
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#define GDMA_CHANNEL_MEM 8
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/* Generic DMA Controller */
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/* GDMA Channel n Source Address */
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#define GDMASA(n) (0x00 + 0x10*n)
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/* GDMA Channel n Destination Address */
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#define GDMADA(n) (0x04 + 0x10*n)
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/* GDMA Channel n Control Register 0 */
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#define GDMACT0(n) (0x08 + 0x10*n)
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#define GDMACT0_TR_COUNT_MASK 0x0fff0000
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#define GDMACT0_TR_COUNT_SHIFT 16
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#define GDMACT0_SRC_CHAN_SHIFT 12
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#define GDMACT0_SRC_CHAN_MASK 0x0000f000
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#define GDMACT0_DST_CHAN_SHIFT 8
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#define GDMACT0_DST_CHAN_MASK 0x00000f00
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#define GDMACT0_SRC_BURST_MODE (1<<7)
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#define GDMACT0_DST_BURST_MODE (1<<6)
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#define GDMACT0_BURST_SIZE_SHIFT 3
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#define GDMACT0_BURST_SIZE_MASK 0x00000038
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#define GDMACT0_BURST_SIZE_1 0
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#define GDMACT0_BURST_SIZE_2 1
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#define GDMACT0_BURST_SIZE_4 2
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#define GDMACT0_BURST_SIZE_8 3
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#define GDMACT0_BURST_SIZE_16 4
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#define GDMACT0_DONE_INT_EN (1<<2)
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#define GDMACT0_CHAN_EN (1<<1)
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/*
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* In software mode, the data transfer will start when the Channel Enable bit
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* is set.
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* In hardware mode, the data transfer will start when the DMA Request is
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* asserted.
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*/
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#define GDMACT0_SWMODE (1<<0)
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#endif /* _RT305XREG_H_ */
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