893 lines
20 KiB
C
893 lines
20 KiB
C
/* $FreeBSD$ */
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/* $NecBSD: dp83932subr.c,v 1.5.6.2 1999/10/09 05:47:23 kmatsuda Exp $ */
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/* $NetBSD$ */
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/*
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* Copyright (c) 1997, 1998, 1999
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* Kouichi Matsuda. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Kouichi Matsuda for
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* NetBSD/pc98.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Routines of NEC PC-9801-83, 84, 103, 104, PC-9801N-25 and PC-9801N-J02, J02R
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* Ethernet interface for NetBSD/pc98, ported by Kouichi Matsuda.
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*
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* These cards use National Semiconductor DP83934AVQB as Ethernet Controller
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* and National Semiconductor NS46C46 as (64 * 16 bits) Microwire Serial EEPROM.
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*/
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/*
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* Modified for FreeBSD(98) 4.0 from NetBSD/pc98 1.4.2 by Motomichi Matsuzaki.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/protosw.h>
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#include <sys/socket.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/if_media.h>
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/in_systm.h>
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#include <netinet/in_var.h>
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#include <netinet/ip.h>
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#include <netinet/if_inarp.h>
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#endif
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <dev/snc/dp83932reg.h>
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#include <dev/snc/dp83932var.h>
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#include <dev/snc/if_sncreg.h>
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#include <dev/snc/dp83932subr.h>
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integrate u_int16_t snc_nec16_select_bank
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__P((struct snc_softc *, u_int32_t, u_int32_t));
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/*
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* Interface exists: make available by filling in network interface
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* record. System will initialize the interface when it is ready
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* to accept packets.
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*/
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int
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sncsetup(sc, lladdr)
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struct snc_softc *sc;
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u_int8_t *lladdr;
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{
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u_int32_t p, pp;
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int i;
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int offset;
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/*
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* Put the pup in reset mode (sncinit() will fix it later),
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* stop the timer, disable all interrupts and clear any interrupts.
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*/
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NIC_PUT(sc, SNCR_CR, CR_STP);
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wbflush();
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NIC_PUT(sc, SNCR_CR, CR_RST);
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wbflush();
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NIC_PUT(sc, SNCR_IMR, 0);
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wbflush();
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NIC_PUT(sc, SNCR_ISR, ISR_ALL);
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wbflush();
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/*
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* because the SONIC is basically 16bit device it 'concatenates'
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* a higher buffer address to a 16 bit offset--this will cause wrap
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* around problems near the end of 64k !!
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*/
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p = pp = 0;
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for (i = 0; i < NRRA; i++) {
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sc->v_rra[i] = SONIC_GETDMA(p);
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p += RXRSRC_SIZE(sc);
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}
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sc->v_rea = SONIC_GETDMA(p);
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p = SOALIGN(sc, p);
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sc->v_cda = SONIC_GETDMA(p);
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p += CDA_SIZE(sc);
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p = SOALIGN(sc, p);
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for (i = 0; i < NTDA; i++) {
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struct mtd *mtdp = &sc->mtda[i];
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mtdp->mtd_vtxp = SONIC_GETDMA(p);
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p += TXP_SIZE(sc);
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}
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p = SOALIGN(sc, p);
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if ((p - pp) > NBPG) {
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device_printf (sc->sc_dev, "sizeof RRA (%ld) + CDA (%ld) +"
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"TDA (%ld) > NBPG (%d). Punt!\n",
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(ulong)sc->v_cda - (ulong)sc->v_rra[0],
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(ulong)sc->mtda[0].mtd_vtxp - (ulong)sc->v_cda,
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(ulong)p - (ulong)sc->mtda[0].mtd_vtxp,
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NBPG);
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return(1);
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}
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p = pp + NBPG;
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pp = p;
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sc->sc_nrda = NBPG / RXPKT_SIZE(sc);
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sc->v_rda = SONIC_GETDMA(p);
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p = pp + NBPG;
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for (i = 0; i < NRBA; i++) {
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sc->rbuf[i] = p;
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p += NBPG;
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}
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pp = p;
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offset = TXBSIZE;
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for (i = 0; i < NTDA; i++) {
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struct mtd *mtdp = &sc->mtda[i];
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mtdp->mtd_vbuf = SONIC_GETDMA(p);
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offset += TXBSIZE;
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if (offset < NBPG) {
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p += TXBSIZE;
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} else {
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p = pp + NBPG;
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pp = p;
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offset = TXBSIZE;
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}
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}
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return (0);
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}
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/*
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* miscellaneous NEC/SONIC detect functions.
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*/
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/*
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* check if a specified irq is acceptable.
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*/
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u_int8_t
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snc_nec16_validate_irq(irq)
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int irq;
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{
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const u_int8_t encoded_irq[16] = {
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-1, -1, -1, 0, -1, 1, 2, -1, -1, 3, 4, -1, 5, 6, -1, -1
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};
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return encoded_irq[irq];
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}
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/*
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* specify irq to board.
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*/
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int
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snc_nec16_register_irq(sc, irq)
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struct snc_softc *sc;
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int irq;
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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u_int8_t encoded_irq;
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encoded_irq = snc_nec16_validate_irq(irq);
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if (encoded_irq == (u_int8_t) -1) {
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printf("snc_nec16_register_irq: unsupported irq (%d)\n", irq);
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return 0;
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}
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/* select SNECR_IRQSEL register */
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bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_IRQSEL);
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/* write encoded irq value */
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bus_space_write_1(iot, ioh, SNEC_CTRLB, encoded_irq);
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return 1;
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}
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/*
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* check if a specified memory base address is acceptable.
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*/
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int
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snc_nec16_validate_mem(maddr)
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int maddr;
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{
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/* Check on Normal mode with max range, only */
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if ((maddr & ~0x1E000) != 0xC0000) {
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printf("snc_nec16_validate_mem: "
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"unsupported window base (0x%x)\n", maddr);
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return 0;
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}
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return 1;
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}
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/*
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* specify memory base address to board and map to first bank.
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*/
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int
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snc_nec16_register_mem(sc, maddr)
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struct snc_softc *sc;
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int maddr;
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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if (snc_nec16_validate_mem(maddr) == 0)
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return 0;
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/* select SNECR_MEMSEL register */
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bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMSEL);
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/* write encoded memory base select value */
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bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_MEMSEL_PHYS2EN(maddr));
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/*
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* set current bank to 0 (bottom) and map
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*/
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/* select SNECR_MEMBS register */
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bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
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/* select new bank */
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bus_space_write_1(iot, ioh, SNEC_CTRLB,
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SNECR_MEMBS_B2EB(0) | SNECR_MEMBS_BSEN);
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/* set current bank to 0 */
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sc->curbank = 0;
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return 1;
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}
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int
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snc_nec16_check_memory(iot, ioh, memt, memh)
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bus_space_tag_t iot;
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bus_space_handle_t ioh;
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bus_space_tag_t memt;
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bus_space_handle_t memh;
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{
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u_int16_t val;
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int i, j;
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val = 0;
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for (i = 0; i < SNEC_NBANK; i++) {
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/* select new bank */
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bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
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bus_space_write_1(iot, ioh, SNEC_CTRLB,
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SNECR_MEMBS_B2EB(i) | SNECR_MEMBS_BSEN);
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/* write test pattern */
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for (j = 0; j < SNEC_NMEMS / 2; j++) {
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bus_space_write_2(memt, memh, j * 2, val + j);
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}
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val += 0x1000;
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}
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val = 0;
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for (i = 0; i < SNEC_NBANK; i++) {
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/* select new bank */
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bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
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bus_space_write_1(iot, ioh, SNEC_CTRLB,
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SNECR_MEMBS_B2EB(i) | SNECR_MEMBS_BSEN);
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/* read test pattern */
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for (j = 0; j < SNEC_NMEMS / 2; j++) {
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if (bus_space_read_2(memt, memh, j * 2) != val + j)
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break;
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}
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if (j < SNEC_NMEMS / 2) {
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printf("snc_nec16_check_memory: "
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"memory check failed at 0x%04x%04x"
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"val 0x%04x != expected 0x%04x\n", i, j,
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bus_space_read_2(memt, memh, j * 2),
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val + j);
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return 0;
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}
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val += 0x1000;
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}
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/* zero clear mem */
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for (i = 0; i < SNEC_NBANK; i++) {
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/* select new bank */
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bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
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bus_space_write_1(iot, ioh, SNEC_CTRLB,
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SNECR_MEMBS_B2EB(i) | SNECR_MEMBS_BSEN);
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bus_space_set_region_4(memt, memh, 0, 0, SNEC_NMEMS >> 2);
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}
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/* again read test if these are 0 */
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for (i = 0; i < SNEC_NBANK; i++) {
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/* select new bank */
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bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
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bus_space_write_1(iot, ioh, SNEC_CTRLB,
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SNECR_MEMBS_B2EB(i) | SNECR_MEMBS_BSEN);
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/* check if cleared */
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for (j = 0; j < SNEC_NMEMS; j += 2) {
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if (bus_space_read_2(memt, memh, j) != 0)
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break;
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}
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if (j != SNEC_NMEMS) {
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printf("snc_nec16_check_memory: "
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"memory zero clear failed at 0x%04x%04x\n", i, j);
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return 0;
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}
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}
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return 1;
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}
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int
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snc_nec16_detectsubr(iot, ioh, memt, memh, irq, maddr, type)
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bus_space_tag_t iot;
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bus_space_handle_t ioh;
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bus_space_tag_t memt;
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bus_space_handle_t memh;
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int irq;
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int maddr;
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u_int8_t type;
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{
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u_int16_t cr;
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u_int8_t ident;
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int rv = 0;
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if (snc_nec16_validate_irq(irq) == (u_int8_t) -1)
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return 0;
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/* XXX: maddr already checked */
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if (snc_nec16_validate_mem(maddr) == 0)
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return 0;
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bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_IDENT);
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ident = bus_space_read_1(iot, ioh, SNEC_CTRLB);
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if (ident == 0xff || ident == 0x00) {
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/* not found */
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return 0;
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}
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switch (type) {
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case SNEC_TYPE_LEGACY:
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rv = (ident == SNECR_IDENT_LEGACY_CBUS);
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break;
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case SNEC_TYPE_PNP:
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rv = ((ident == SNECR_IDENT_PNP_CBUS) ||
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(ident == SNECR_IDENT_PNP_PCMCIABUS));
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break;
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default:
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break;
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}
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if (rv == 0) {
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printf("snc_nec16_detectsubr: parent bus mismatch\n");
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return 0;
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}
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/* select SONIC register SNCR_CR */
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bus_space_write_1(iot, ioh, SNEC_ADDR, SNCR_CR);
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bus_space_write_2(iot, ioh, SNEC_CTRL, CR_RXDIS | CR_STP | CR_RST);
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delay(400);
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cr = bus_space_read_2(iot, ioh, SNEC_CTRL);
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if (cr != (CR_RXDIS | CR_STP | CR_RST)) {
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#ifdef DIAGNOSTIC
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printf("snc_nec16_detectsubr: card reset failed, cr = 0x%04x\n",
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cr);
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#endif
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return 0;
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}
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if (snc_nec16_check_memory(iot, ioh, memt, memh) == 0)
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return 0;
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return 1;
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}
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/* XXX */
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#define SNC_VENDOR_NEC 0x00004c
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#define SNC_NEC_SERIES_LEGACY_CBUS 0xa5
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#define SNC_NEC_SERIES_PNP_PCMCIA 0xd5
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#define SNC_NEC_SERIES_PNP_PCMCIA2 0x6d /* XXX */
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#define SNC_NEC_SERIES_PNP_CBUS 0x0d
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#define SNC_NEC_SERIES_PNP_CBUS2 0x3d
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u_int8_t *
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snc_nec16_detect_type(myea)
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u_int8_t *myea;
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{
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u_int32_t vendor = (myea[0] << 16) | (myea[1] << 8) | myea[2];
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u_int8_t series = myea[3];
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u_int8_t type = myea[4] & 0x80;
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u_int8_t *typestr;
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switch (vendor) {
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case SNC_VENDOR_NEC:
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switch (series) {
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case SNC_NEC_SERIES_LEGACY_CBUS:
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if (type)
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typestr = "NEC PC-9801-84";
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else
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typestr = "NEC PC-9801-83";
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break;
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case SNC_NEC_SERIES_PNP_CBUS:
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case SNC_NEC_SERIES_PNP_CBUS2:
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if (type)
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typestr = "NEC PC-9801-104";
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else
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typestr = "NEC PC-9801-103";
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break;
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case SNC_NEC_SERIES_PNP_PCMCIA:
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case SNC_NEC_SERIES_PNP_PCMCIA2:
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/* XXX: right ? */
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if (type)
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typestr = "NEC PC-9801N-J02R";
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else
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typestr = "NEC PC-9801N-J02";
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break;
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default:
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typestr = "NEC unknown (PC-9801N-25?)";
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break;
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}
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break;
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default:
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typestr = "unknown (3rd vendor?)";
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break;
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}
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return typestr;
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}
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int
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snc_nec16_get_enaddr(iot, ioh, myea)
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bus_space_tag_t iot;
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bus_space_handle_t ioh;
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u_int8_t *myea;
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{
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u_int8_t eeprom[SNEC_EEPROM_SIZE];
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u_int8_t rom_sum, sum = 0x00;
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int i;
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snc_nec16_read_eeprom(iot, ioh, eeprom);
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for (i = SNEC_EEPROM_KEY0; i < SNEC_EEPROM_CKSUM; i++) {
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sum = sum ^ eeprom[i];
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}
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rom_sum = eeprom[SNEC_EEPROM_CKSUM];
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if (sum != rom_sum) {
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printf("snc_nec16_get_enaddr: "
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"checksum mismatch; calculated %02x != read %02x",
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sum, rom_sum);
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return 0;
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}
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for (i = 0; i < ETHER_ADDR_LEN; i++)
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myea[i] = eeprom[SNEC_EEPROM_SA0 + i];
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return 1;
|
|
}
|
|
|
|
/*
|
|
* read from NEC/SONIC NIC register.
|
|
*/
|
|
u_int16_t
|
|
snc_nec16_nic_get(sc, reg)
|
|
struct snc_softc *sc;
|
|
u_int8_t reg;
|
|
{
|
|
u_int16_t val;
|
|
|
|
/* select SONIC register */
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, SNEC_ADDR, reg);
|
|
val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, SNEC_CTRL);
|
|
|
|
return val;
|
|
}
|
|
|
|
/*
|
|
* write to NEC/SONIC NIC register.
|
|
*/
|
|
void
|
|
snc_nec16_nic_put(sc, reg, val)
|
|
struct snc_softc *sc;
|
|
u_int8_t reg;
|
|
u_int16_t val;
|
|
{
|
|
|
|
/* select SONIC register */
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, SNEC_ADDR, reg);
|
|
bus_space_write_2(sc->sc_iot, sc->sc_ioh, SNEC_CTRL, val);
|
|
}
|
|
|
|
|
|
/*
|
|
* select memory bank and map
|
|
* where exists specified (internal buffer memory) offset.
|
|
*/
|
|
integrate u_int16_t
|
|
snc_nec16_select_bank(sc, base, offset)
|
|
struct snc_softc *sc;
|
|
u_int32_t base;
|
|
u_int32_t offset;
|
|
{
|
|
bus_space_tag_t iot = sc->sc_iot;
|
|
bus_space_handle_t ioh = sc->sc_ioh;
|
|
u_int8_t bank;
|
|
u_int16_t noffset;
|
|
|
|
/* bitmode is fixed to 16 bit. */
|
|
bank = (base + offset * 2) >> 13;
|
|
noffset = (base + offset * 2) & (SNEC_NMEMS - 1);
|
|
|
|
#ifdef SNCDEBUG
|
|
if (noffset % 2) {
|
|
device_printf(sc->sc_dev, "noffset is odd (0x%04x)\n",
|
|
noffset);
|
|
}
|
|
#endif /* SNCDEBUG */
|
|
|
|
if (sc->curbank != bank) {
|
|
/* select SNECR_MEMBS register */
|
|
bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
|
|
/* select new bank */
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB,
|
|
SNECR_MEMBS_B2EB(bank) | SNECR_MEMBS_BSEN);
|
|
/* update current bank */
|
|
sc->curbank = bank;
|
|
}
|
|
|
|
return noffset;
|
|
}
|
|
|
|
/*
|
|
* write to SONIC descriptors.
|
|
*/
|
|
void
|
|
snc_nec16_writetodesc(sc, base, offset, val)
|
|
struct snc_softc *sc;
|
|
u_int32_t base;
|
|
u_int32_t offset;
|
|
u_int16_t val;
|
|
{
|
|
bus_space_tag_t memt = sc->sc_memt;
|
|
bus_space_handle_t memh = sc->sc_memh;
|
|
u_int16_t noffset;
|
|
|
|
noffset = snc_nec16_select_bank(sc, base, offset);
|
|
|
|
bus_space_write_2(memt, memh, noffset, val);
|
|
}
|
|
|
|
/*
|
|
* read from SONIC descriptors.
|
|
*/
|
|
u_int16_t
|
|
snc_nec16_readfromdesc(sc, base, offset)
|
|
struct snc_softc *sc;
|
|
u_int32_t base;
|
|
u_int32_t offset;
|
|
{
|
|
bus_space_tag_t memt = sc->sc_memt;
|
|
bus_space_handle_t memh = sc->sc_memh;
|
|
u_int16_t noffset;
|
|
|
|
noffset = snc_nec16_select_bank(sc, base, offset);
|
|
|
|
return bus_space_read_2(memt, memh, noffset);
|
|
}
|
|
|
|
/*
|
|
* read from SONIC data buffer.
|
|
*/
|
|
void
|
|
snc_nec16_copyfrombuf(sc, dst, offset, size)
|
|
struct snc_softc *sc;
|
|
void *dst;
|
|
u_int32_t offset;
|
|
size_t size;
|
|
{
|
|
bus_space_tag_t memt = sc->sc_memt;
|
|
bus_space_handle_t memh = sc->sc_memh;
|
|
u_int16_t noffset;
|
|
u_int8_t* bptr = dst;
|
|
|
|
noffset = snc_nec16_select_bank(sc, offset, 0);
|
|
|
|
/* XXX: should check if offset + size < 0x2000. */
|
|
|
|
bus_space_barrier(memt, memh, noffset, size,
|
|
BUS_SPACE_BARRIER_READ);
|
|
|
|
if (size > 3) {
|
|
if (noffset & 3) {
|
|
size_t asize = (~noffset & 3);
|
|
|
|
bus_space_read_region_1(memt, memh, noffset,
|
|
bptr, asize);
|
|
bptr += asize;
|
|
noffset += asize;
|
|
size -= asize;
|
|
}
|
|
bus_space_read_region_4(memt, memh, noffset,
|
|
(u_int32_t *) bptr, size >> 2);
|
|
bptr += size & ~3;
|
|
noffset += size & ~3;
|
|
size &= 3;
|
|
}
|
|
if (size)
|
|
bus_space_read_region_1(memt, memh, noffset, bptr, size);
|
|
}
|
|
|
|
/*
|
|
* write to SONIC data buffer.
|
|
*/
|
|
void
|
|
snc_nec16_copytobuf(sc, src, offset, size)
|
|
struct snc_softc *sc;
|
|
void *src;
|
|
u_int32_t offset;
|
|
size_t size;
|
|
{
|
|
bus_space_tag_t memt = sc->sc_memt;
|
|
bus_space_handle_t memh = sc->sc_memh;
|
|
u_int16_t noffset, onoffset;
|
|
size_t osize = size;
|
|
u_int8_t* bptr = src;
|
|
|
|
noffset = snc_nec16_select_bank(sc, offset, 0);
|
|
onoffset = noffset;
|
|
|
|
/* XXX: should check if offset + size < 0x2000. */
|
|
|
|
if (size > 3) {
|
|
if (noffset & 3) {
|
|
size_t asize = (~noffset & 3);
|
|
|
|
bus_space_write_region_1(memt, memh, noffset,
|
|
bptr, asize);
|
|
bptr += asize;
|
|
noffset += asize;
|
|
size -= asize;
|
|
}
|
|
bus_space_write_region_4(memt, memh, noffset,
|
|
(u_int32_t *)bptr, size >> 2);
|
|
bptr += size & ~3;
|
|
noffset += size & ~3;
|
|
size -= size & ~3;
|
|
}
|
|
if (size)
|
|
bus_space_write_region_1(memt, memh, noffset, bptr, size);
|
|
|
|
bus_space_barrier(memt, memh, onoffset, osize,
|
|
BUS_SPACE_BARRIER_WRITE);
|
|
}
|
|
|
|
/*
|
|
* write (fill) 0 to SONIC data buffer.
|
|
*/
|
|
void
|
|
snc_nec16_zerobuf(sc, offset, size)
|
|
struct snc_softc *sc;
|
|
u_int32_t offset;
|
|
size_t size;
|
|
{
|
|
bus_space_tag_t memt = sc->sc_memt;
|
|
bus_space_handle_t memh = sc->sc_memh;
|
|
u_int16_t noffset, onoffset;
|
|
size_t osize = size;
|
|
|
|
noffset = snc_nec16_select_bank(sc, offset, 0);
|
|
onoffset = noffset;
|
|
|
|
/* XXX: should check if offset + size < 0x2000. */
|
|
|
|
if (size > 3) {
|
|
if (noffset & 3) {
|
|
size_t asize = (~noffset & 3);
|
|
|
|
bus_space_set_region_1(memt, memh, noffset, 0, asize);
|
|
noffset += asize;
|
|
size -= asize;
|
|
}
|
|
bus_space_set_region_4(memt, memh, noffset, 0, size >> 2);
|
|
noffset += size & ~3;
|
|
size -= size & ~3;
|
|
}
|
|
if (size)
|
|
bus_space_set_region_1(memt, memh, noffset, 0, size);
|
|
|
|
bus_space_barrier(memt, memh, onoffset, osize,
|
|
BUS_SPACE_BARRIER_WRITE);
|
|
}
|
|
|
|
|
|
/*
|
|
* Routines to read bytes sequentially from EEPROM through NEC PC-9801-83,
|
|
* 84, 103, 104, PC-9801N-25 and PC-9801N-J02, J02R for NetBSD/pc98.
|
|
* Ported by Kouichi Matsuda.
|
|
*
|
|
* This algorism is generic to read data sequentially from 4-Wire
|
|
* Microwire Serial EEPROM.
|
|
*/
|
|
|
|
#define SNEC_EEP_DELAY 1000
|
|
|
|
void
|
|
snc_nec16_read_eeprom(iot, ioh, data)
|
|
bus_space_tag_t iot;
|
|
bus_space_handle_t ioh;
|
|
u_int8_t *data;
|
|
{
|
|
u_int8_t n, val, bit;
|
|
|
|
/* Read bytes from EEPROM; two bytes per an iteration. */
|
|
for (n = 0; n < SNEC_EEPROM_SIZE / 2; n++) {
|
|
/* select SNECR_EEP */
|
|
bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_EEP);
|
|
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB, 0x00);
|
|
delay(SNEC_EEP_DELAY);
|
|
|
|
/* Start EEPROM access. */
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS);
|
|
delay(SNEC_EEP_DELAY);
|
|
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB,
|
|
SNECR_EEP_CS | SNECR_EEP_SK);
|
|
delay(SNEC_EEP_DELAY);
|
|
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB,
|
|
SNECR_EEP_CS | SNECR_EEP_DI);
|
|
delay(SNEC_EEP_DELAY);
|
|
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB,
|
|
SNECR_EEP_CS | SNECR_EEP_SK | SNECR_EEP_DI);
|
|
delay(SNEC_EEP_DELAY);
|
|
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB,
|
|
SNECR_EEP_CS | SNECR_EEP_DI);
|
|
delay(SNEC_EEP_DELAY);
|
|
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB,
|
|
SNECR_EEP_CS | SNECR_EEP_SK | SNECR_EEP_DI);
|
|
delay(SNEC_EEP_DELAY);
|
|
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS);
|
|
delay(SNEC_EEP_DELAY);
|
|
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB,
|
|
SNECR_EEP_CS | SNECR_EEP_SK);
|
|
delay(SNEC_EEP_DELAY);
|
|
|
|
/* Pass the iteration count to the chip. */
|
|
for (bit = 0x20; bit != 0x00; bit >>= 1) {
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS |
|
|
((n & bit) ? SNECR_EEP_DI : 0x00));
|
|
delay(SNEC_EEP_DELAY);
|
|
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB,
|
|
SNECR_EEP_CS | SNECR_EEP_SK |
|
|
((n & bit) ? SNECR_EEP_DI : 0x00));
|
|
delay(SNEC_EEP_DELAY);
|
|
}
|
|
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS);
|
|
(void) bus_space_read_1(iot, ioh, SNEC_CTRLB); /* ACK */
|
|
delay(SNEC_EEP_DELAY);
|
|
|
|
/* Read a byte. */
|
|
val = 0;
|
|
for (bit = 0x80; bit != 0x00; bit >>= 1) {
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB,
|
|
SNECR_EEP_CS | SNECR_EEP_SK);
|
|
delay(SNEC_EEP_DELAY);
|
|
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS);
|
|
|
|
if (bus_space_read_1(iot, ioh, SNEC_CTRLB) & SNECR_EEP_DO)
|
|
val |= bit;
|
|
}
|
|
*data++ = val;
|
|
|
|
/* Read one more byte. */
|
|
val = 0;
|
|
for (bit = 0x80; bit != 0x00; bit >>= 1) {
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB,
|
|
SNECR_EEP_CS | SNECR_EEP_SK);
|
|
delay(SNEC_EEP_DELAY);
|
|
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS);
|
|
|
|
if (bus_space_read_1(iot, ioh, SNEC_CTRLB) & SNECR_EEP_DO)
|
|
val |= bit;
|
|
}
|
|
*data++ = val;
|
|
|
|
bus_space_write_1(iot, ioh, SNEC_CTRLB, 0x00);
|
|
delay(SNEC_EEP_DELAY);
|
|
}
|
|
|
|
#ifdef SNCDEBUG
|
|
/* Report what we got. */
|
|
data -= SNEC_EEPROM_SIZE;
|
|
log(LOG_INFO, "%s: EEPROM:"
|
|
" %02x%02x%02x%02x %02x%02x%02x%02x -"
|
|
" %02x%02x%02x%02x %02x%02x%02x%02x -"
|
|
" %02x%02x%02x%02x %02x%02x%02x%02x -"
|
|
" %02x%02x%02x%02x %02x%02x%02x%02x\n",
|
|
"snc_nec16_read_eeprom",
|
|
data[ 0], data[ 1], data[ 2], data[ 3],
|
|
data[ 4], data[ 5], data[ 6], data[ 7],
|
|
data[ 8], data[ 9], data[10], data[11],
|
|
data[12], data[13], data[14], data[15],
|
|
data[16], data[17], data[18], data[19],
|
|
data[20], data[21], data[22], data[23],
|
|
data[24], data[25], data[26], data[27],
|
|
data[28], data[29], data[30], data[31]);
|
|
#endif
|
|
}
|
|
|
|
#ifdef SNCDEBUG
|
|
void
|
|
snc_nec16_dump_reg(iot, ioh)
|
|
bus_space_tag_t iot;
|
|
bus_space_handle_t ioh;
|
|
{
|
|
u_int8_t n;
|
|
u_int16_t val;
|
|
|
|
printf("SONIC registers (word):");
|
|
for (n = 0; n < SNC_NREGS; n++) {
|
|
/* select required SONIC register */
|
|
bus_space_write_1(iot, ioh, SNEC_ADDR, n);
|
|
delay(10);
|
|
val = bus_space_read_2(iot, ioh, SNEC_CTRL);
|
|
if ((n % 0x10) == 0)
|
|
printf("\n%04x ", val);
|
|
else
|
|
printf("%04x ", val);
|
|
}
|
|
printf("\n");
|
|
|
|
printf("NEC/SONIC registers (byte):\n");
|
|
for (n = SNECR_MEMBS; n <= SNECR_IDENT; n += 2) {
|
|
/* select required SONIC register */
|
|
bus_space_write_1(iot, ioh, SNEC_ADDR, n);
|
|
delay(10);
|
|
val = (u_int16_t) bus_space_read_1(iot, ioh, SNEC_CTRLB);
|
|
printf("%04x ", val);
|
|
}
|
|
printf("\n");
|
|
}
|
|
|
|
#endif /* SNCDEBUG */
|