0ecc2ff0e8
Fixes: - flow control - don't override user value on re-init - fix to make 1G optics work correctly - change to interrupt enabling - some bits were incorrect for certain hardware. - certain stats fixes, remove a duplicate increment of ierror, thanks to Scott Long for pointing these out. - shared code link interface changed, requiring some core code changes to accomodate this. - add an m_adj() to ETHER_ALIGN on the recieve side, this was requested by Mike Karels, thanks Mike. - Multicast code corrections also thanks to Mike Karels.
177 lines
8.2 KiB
C
177 lines
8.2 KiB
C
/******************************************************************************
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Copyright (c) 2001-2013, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#ifndef _IXGBE_API_H_
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#define _IXGBE_API_H_
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#include "ixgbe_type.h"
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s32 ixgbe_init_shared_code(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw);
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extern s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw);
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s32 ixgbe_set_mac_type(struct ixgbe_hw *hw);
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s32 ixgbe_init_hw(struct ixgbe_hw *hw);
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s32 ixgbe_reset_hw(struct ixgbe_hw *hw);
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s32 ixgbe_start_hw(struct ixgbe_hw *hw);
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void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw);
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s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw);
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enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw);
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s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr);
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s32 ixgbe_get_bus_info(struct ixgbe_hw *hw);
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u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw);
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u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw);
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s32 ixgbe_stop_adapter(struct ixgbe_hw *hw);
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s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num);
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s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);
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s32 ixgbe_identify_phy(struct ixgbe_hw *hw);
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s32 ixgbe_reset_phy(struct ixgbe_hw *hw);
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s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
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u16 *phy_data);
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s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
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u16 phy_data);
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s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
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s32 ixgbe_check_phy_link(struct ixgbe_hw *hw,
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ixgbe_link_speed *speed,
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bool *link_up);
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s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw,
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ixgbe_link_speed speed,
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bool autoneg_wait_to_complete);
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void ixgbe_disable_tx_laser(struct ixgbe_hw *hw);
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void ixgbe_enable_tx_laser(struct ixgbe_hw *hw);
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void ixgbe_flap_tx_laser(struct ixgbe_hw *hw);
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s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
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bool autoneg_wait_to_complete);
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s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
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bool *link_up, bool link_up_wait_to_complete);
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s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
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bool *autoneg);
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s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw);
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s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data);
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s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
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u16 words, u16 *data);
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s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);
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s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
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u16 words, u16 *data);
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s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);
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s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw);
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s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
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s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
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u32 enable_addr);
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s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index);
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s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
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s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq);
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s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
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s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);
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u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw);
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s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
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u32 addr_count, ixgbe_mc_addr_itr func);
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s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
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u32 mc_addr_count, ixgbe_mc_addr_itr func,
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bool clear);
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void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq);
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s32 ixgbe_enable_mc(struct ixgbe_hw *hw);
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s32 ixgbe_disable_mc(struct ixgbe_hw *hw);
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s32 ixgbe_clear_vfta(struct ixgbe_hw *hw);
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s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,
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u32 vind, bool vlan_on);
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s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind,
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bool vlan_on, bool *vfta_changed);
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s32 ixgbe_fc_enable(struct ixgbe_hw *hw);
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s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
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u8 ver);
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void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);
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s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw,
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u16 *firmware_version);
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s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);
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s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);
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s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw);
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s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data);
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u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw);
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s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval);
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s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw);
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s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw);
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s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
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s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
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s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
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s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_hash_dword input,
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union ixgbe_atr_hash_dword common,
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u8 queue);
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s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input_mask);
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s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input,
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u16 soft_id, u8 queue);
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s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input,
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u16 soft_id);
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s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
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union ixgbe_atr_input *input,
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union ixgbe_atr_input *mask,
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u16 soft_id,
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u8 queue);
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void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
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union ixgbe_atr_input *mask);
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u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
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union ixgbe_atr_hash_dword common);
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bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
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s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
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u8 *data);
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s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
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u8 data);
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s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);
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s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
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s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
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s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps);
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s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
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void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
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s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
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u16 *wwpn_prefix);
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s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);
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#endif /* _IXGBE_API_H_ */
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