0dd51f62a8
- Change lines referring to kernel configuration file:
device foo0 at isa port xxx irq yyy...
to
device foo
Describe resource "hints" in /boot/device.hints.
- Try to describe resource allocation and probe/attach behavior in the
newbus framework.
299 lines
10 KiB
Groff
299 lines
10 KiB
Groff
.\"
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.\" Copyright (c) 1995, 1996, 1997, 1998, 2000
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.\" Justin T. Gibbs. All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\" 3. The name of the author may not be used to endorse or promote products
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.\" derived from this software without specific prior written permission.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd February 13, 2000
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.Dt AHC 4
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.Os
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.Sh NAME
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.Nm ahc
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.Nd Adaptec VL/EISA/PCI SCSI host adapter driver
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.Sh SYNOPSIS
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For one or more VL/EISA cards:
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.Cd device eisa
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.Cd device ahc
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.Pp
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For one or more PCI cards:
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.Cd device pci
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.Cd device ahc
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.Pp
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To allow PCI adapters to use memory mapped I/O if enabled:
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.Cd options AHC_ALLOW_MEMIO
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.Pp
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To configure one or more controllers to assume the target role:
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.Cd options AHC_TMODE_ENABLE <bitmask of units>
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.Pp
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For one or more SCSI busses:
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.Cd device scbus
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.Sh DESCRIPTION
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This driver provides access to the
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.Tn SCSI
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bus(es) connected to Adaptec
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.Tn AIC7770 ,
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.Tn AIC7850 ,
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.Tn AIC7860 ,
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.Tn AIC7870 ,
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.Tn AIC7880 ,
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.Tn AIC7890 ,
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.Tn AIC7891 ,
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.Tn AIC7892 ,
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.Tn AIC7895 ,
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.Tn AIC7896 ,
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.Tn AIC7897
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and
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.Tn AIC7899
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host adapter chips.
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These chips are found on many motherboards as well as the following
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Adaptec SCSI controller cards:
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.Tn 274X(W) ,
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.Tn 274X(T) ,
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.Tn 284X ,
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.Tn 2910 ,
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.Tn 2915 ,
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.Tn 2920 ,
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.Tn 2930C ,
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.Tn 2930U2 ,
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.Tn 2940 ,
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.Tn 2940U ,
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.Tn 2940AU ,
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.Tn 2940UW ,
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.Tn 2940UW Dual ,
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.Tn 2940UW Pro ,
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.Tn 2940U2W ,
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.Tn 2940U2B ,
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.Tn 2950U2W ,
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.Tn 2950U2B ,
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.Tn 19160B ,
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.Tn 29160B ,
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.Tn 29160N ,
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.Tn 3940 ,
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.Tn 3940U ,
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.Tn 3940AU ,
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.Tn 3940UW ,
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.Tn 3940AUW ,
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.Tn 3940U2W ,
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.Tn 3950U2 ,
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.Tn 3960 ,
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.Tn 39160 ,
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.Tn 3985 ,
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and
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.Tn 4944UW .
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.Pp
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Driver features include support for twin and wide busses,
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fast, ultra or ultra2 synchronous transfers depending on controller type,
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tagged queueing, SCB paging, and target mode.
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.Pp
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Memory mapped I/O can be enabled for PCI devices with the
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.Dq Dv AHC_ALLOW_MEMIO
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configuration option.
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Memory mapped I/O is more efficient than the alternative, programmed I/O.
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Most PCI BIOSes will map devices so that either technique for communicating
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with the card is available.
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In some cases,
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usually when the PCI device is sitting behind a PCI->PCI bridge,
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the BIOS may fail to properly initialize the chip for memory mapped I/O.
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The typical symptom of this problem is a system hang if memory mapped I/O
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is attempted.
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Most modern motherboards perform the initialization correctly and work fine
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with this option enabled.
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.Pp
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Individual controllers may be configured to operate in the target role
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through the
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.Dq Dv AHC_TMODE_ENABLE
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configuration option. The value assigned to this option should be a bitmap
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of all units where target mode is desired.
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For example, a value of 0x25, would enable target mode on units 0, 2, and 5.
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.Pp
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Per target configuration performed in the
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.Tn SCSI-Select
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menu, accessible at boot
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in
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.No non- Ns Tn EISA
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models,
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or through an
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.Tn EISA
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configuration utility for
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.Tn EISA
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models,
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is honored by this driver.
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This includes synchronous/asynchronous transfers,
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maximum synchronous negotiation rate,
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wide transfers,
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disconnection,
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the host adapter's SCSI ID,
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and,
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in the case of
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.Tn EISA
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Twin Channel controllers,
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the primary channel selection.
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For systems that store non-volatile settings in a system specific manner
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rather than a serial eeprom directly connected to the aic7xxx controller,
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the
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.Tn BIOS
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must be enabled for the driver to access this information.
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This restriction applies to all
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.Tn EISA
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and many motherboard configurations.
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.Pp
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Note that I/O addresses are determined automatically by the probe routines,
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but care should be taken when using a 284x
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.Pq Tn VESA No local bus controller
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in an
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.Tn EISA
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system. The jumpers setting the I/O area for the 284x should match the
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.Tn EISA
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slot into which the card is inserted to prevent conflicts with other
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.Tn EISA
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cards.
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.Pp
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Performance and feature sets vary throughout the aic7xxx product line.
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The following table provides a comparison of the different chips supported
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by the
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.Nm
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driver. Note that wide and twin channel features, although always supported
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by a particular chip, may be disabled in a particular motherboard or card
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design.
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.Pp
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.Bd -ragged -offset indent
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.Bl -column "aic7770 " "10 " "EISA/VL " "10MHz " "16bit " "SCBs " Features
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.Em "Chip MIPS Bus MaxSync MaxWidth SCBs Features"
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aic7770 10 EISA/VL 10MHz 16Bit 4 1
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aic7850 10 PCI/32 10MHz 8Bit 3
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aic7860 10 PCI/32 20MHz 8Bit 3
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aic7870 10 PCI/32 10MHz 16Bit 16
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aic7880 10 PCI/32 20MHz 16Bit 16
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aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
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aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
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aic7892 20 PCI/64 80MHz 16Bit 16 3 4 5 6 7 8
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aic7895 15 PCI/32 20MHz 16Bit 16 2 3 4 5
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aic7895C 15 PCI/32 20MHz 16Bit 16 2 3 4 5 8
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aic7896 20 PCI/32 40MHz 16Bit 16 2 3 4 5 6 7 8
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aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 8
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aic7899 20 PCI/64 80MHz 16Bit 16 2 3 4 5 6 7 8
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.El
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.Pp
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.Bl -enum -compact
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.It
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Multiplexed Twin Channel Device - One controller servicing two busses.
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.It
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Multi-function Twin Channel Device - Two controllers on one chip.
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.It
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Command Channel Secondary DMA Engine - Allows scatter gather list and
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SCB prefetch.
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.It
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64 Byte SCB Support - SCSI CDB is embedded in the SCB to eliminate an extra DMA.
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.It
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Block Move Instruction Support - Doubles the speed of certain sequencer
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operations.
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.It
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.Sq Bayonet
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style Scatter Gather Engine - Improves S/G prefetch performance.
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.It
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Queuing Registers - Allows queueing of new transactions without pausing the
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sequencer.
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.It
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Multiple Target IDs - Allows the controller to respond to selection as a
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target on multiple SCSI IDs.
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.El
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.Ed
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.Sh SCSI CONTROL BLOCKS (SCBs)
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Every transaction sent to a device on the SCSI bus is assigned a
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.Sq SCSI Control Block
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(SCB). The SCB contains all of the information required by the
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controller to process a transaction. The chip feature table lists
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the number of SCBs that can be stored in on-chip memory. All chips
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with model numbers greater than or equal to 7870 allow for the on chip
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SCB space to be augmented with external SRAM up to a maximum of 255 SCBs.
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Very few Adaptec controller configurations have external SRAM.
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.Pp
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If external SRAM is not available, SCBs are a limited resource.
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Using the SCBs in a straight forward manner would only allow the dirver to
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handle as many concurrent transactions as there are physical SCBs.
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To fully utilize the SCSI bus and the devices on it,
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requires much more concurrency.
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The solution to this problem is
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.Em SCB Paging ,
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a concept similar to memory paging. SCB paging takes advantage of
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the fact that devices usually disconnect from the SCSI bus for long
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periods of time without talking to the controller. The SCBs
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for disconnected transactions are only of use to the controller
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when the transfer is resumed. When the host queues another transaction
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for the controller to execute, the controller firmware will use a
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free SCB if one is available. Otherwise, the state of the most recently
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disconnected (and therefore most likely to stay disconnected) SCB is
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saved, via dma, to host memory, and the local SCB reused to start
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the new transaction. This allows the controller to queue up to
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255 transactions regardless of the amount of SCB space. Since the
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local SCB space serves as a cache for disconnected transactions, the
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more SCB space available, the less host bus traffic consumed saving
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and restoring SCB data.
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.Sh BUGS
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Some Quantum drives (at least the Empire 2100 and 1080s) will not run on an
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.Tn AIC7870
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Rev B in synchronous mode at 10MHz. Controllers with this problem have a
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42 MHz clock crystal on them and run slightly above 10MHz. This confuses
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the drive and hangs the bus. Setting a maximum synchronous negotiation rate
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of 8MHz in the
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.Tn SCSI-Select
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utility will allow normal operation.
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.Pp
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Double Transition clocking is not yet supported for Ultra160 controllers.
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This limits these controllers to 40MHz or 80MB/s.
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.Pp
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Although the Ultra2 and Ultra160 products have sufficient instruction
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ram space to support both the initiator and target roles concurrently,
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this configuration is disabled in favor of allowing the target role
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to respond on multiple target ids. A method for configuring dual
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role mode should be provided.
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.Pp
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Tagged Queuing is not supported in target mode.
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.Pp
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Reselection in target mode fails to function correctly on all high
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voltage differential boards as shipped by Adaptec. Information on
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how to modify HVD board to work correctly in target mode is available
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from Adaptec.
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.Sh SEE ALSO
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.Xr aha 4 ,
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.Xr ahb 4 ,
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.Xr cd 4 ,
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.Xr da 4 ,
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.Xr sa 4 ,
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.Xr scsi 4
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.Sh AUTHORS
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The
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.Nm
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driver, the
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.Tn AIC7xxx
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sequencer-code assembler,
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and the firmware running on the aic7xxx chips was written by
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.An Justin T. Gibbs .
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.Sh HISTORY
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The
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.Nm
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driver appeared in
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.Fx 2.0 .
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