ae526637c4
Revert r338177, r338176, r338175, r338174, r338172 After long consultations with re@, core members and mmacy, revert these changes. Followup changes will be made to mark them as deprecated and prent a message about where to find the up-to-date driver. Followup commits will be made to make this clear in the installer. Followup commits to reduce POLA in ways we're still exploring. It's anticipated that after the freeze, this will be removed in 13-current (with the residual of the drm2 code copied to sys/arm/dev/drm2 for the TEGRA port's use w/o the intel or radeon drivers). Due to the impending freeze, there was no formal core vote for this. I've been talking to different core members all day, as well as Matt Macey and Glen Barber. Nobody is completely happy, all are grudgingly going along with this. Work is in progress to mitigate the negative effects as much as possible. Requested by: re@ (gjb, rgrimes)
357 lines
12 KiB
C
357 lines
12 KiB
C
/*
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* Copyright © 2008 Keith Packard
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation, and
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* that the name of the copyright holders not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. The copyright holders make no representations
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* about the suitability of this software for any purpose. It is provided "as
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* is" without express or implied warranty.
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*
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
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* OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef _DRM_DP_HELPER_H_
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#define _DRM_DP_HELPER_H_
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/*
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* Unless otherwise noted, all values are from the DP 1.1a spec. Note that
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* DP and DPCD versions are independent. Differences from 1.0 are not noted,
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* 1.0 devices basically don't exist in the wild.
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*
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* Abbreviations, in chronological order:
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*
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* eDP: Embedded DisplayPort version 1
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* DPI: DisplayPort Interoperability Guideline v1.1a
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* 1.2: DisplayPort 1.2
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*
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* 1.2 formally includes both eDP and DPI definitions.
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*/
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#define AUX_NATIVE_WRITE 0x8
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#define AUX_NATIVE_READ 0x9
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#define AUX_I2C_WRITE 0x0
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#define AUX_I2C_READ 0x1
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#define AUX_I2C_STATUS 0x2
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#define AUX_I2C_MOT 0x4
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#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
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#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
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#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
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#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
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#define AUX_I2C_REPLY_ACK (0x0 << 6)
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#define AUX_I2C_REPLY_NACK (0x1 << 6)
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#define AUX_I2C_REPLY_DEFER (0x2 << 6)
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#define AUX_I2C_REPLY_MASK (0x3 << 6)
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/* AUX CH addresses */
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/* DPCD */
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#define DP_DPCD_REV 0x000
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#define DP_MAX_LINK_RATE 0x001
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#define DP_MAX_LANE_COUNT 0x002
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# define DP_MAX_LANE_COUNT_MASK 0x1f
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# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
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# define DP_ENHANCED_FRAME_CAP (1 << 7)
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#define DP_MAX_DOWNSPREAD 0x003
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# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
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#define DP_NORP 0x004
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#define DP_DOWNSTREAMPORT_PRESENT 0x005
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# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
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# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
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/* 00b = DisplayPort */
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/* 01b = Analog */
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/* 10b = TMDS or HDMI */
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/* 11b = Other */
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# define DP_FORMAT_CONVERSION (1 << 3)
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# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
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#define DP_MAIN_LINK_CHANNEL_CODING 0x006
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#define DP_DOWN_STREAM_PORT_COUNT 0x007
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# define DP_PORT_COUNT_MASK 0x0f
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# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
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# define DP_OUI_SUPPORT (1 << 7)
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#define DP_I2C_SPEED_CAP 0x00c /* DPI */
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# define DP_I2C_SPEED_1K 0x01
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# define DP_I2C_SPEED_5K 0x02
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# define DP_I2C_SPEED_10K 0x04
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# define DP_I2C_SPEED_100K 0x08
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# define DP_I2C_SPEED_400K 0x10
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# define DP_I2C_SPEED_1M 0x20
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#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
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#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
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/* Multiple stream transport */
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#define DP_MSTM_CAP 0x021 /* 1.2 */
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# define DP_MST_CAP (1 << 0)
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#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
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# define DP_PSR_IS_SUPPORTED 1
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#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
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# define DP_PSR_NO_TRAIN_ON_EXIT 1
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# define DP_PSR_SETUP_TIME_330 (0 << 1)
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# define DP_PSR_SETUP_TIME_275 (1 << 1)
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# define DP_PSR_SETUP_TIME_220 (2 << 1)
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# define DP_PSR_SETUP_TIME_165 (3 << 1)
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# define DP_PSR_SETUP_TIME_110 (4 << 1)
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# define DP_PSR_SETUP_TIME_55 (5 << 1)
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# define DP_PSR_SETUP_TIME_0 (6 << 1)
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# define DP_PSR_SETUP_TIME_MASK (7 << 1)
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# define DP_PSR_SETUP_TIME_SHIFT 1
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/*
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* 0x80-0x8f describe downstream port capabilities, but there are two layouts
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* based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
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* each port's descriptor is one byte wide. If it was set, each port's is
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* four bytes wide, starting with the one byte from the base info. As of
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* DP interop v1.1a only VGA defines additional detail.
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*/
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/* offset 0 */
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#define DP_DOWNSTREAM_PORT_0 0x80
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# define DP_DS_PORT_TYPE_MASK (7 << 0)
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# define DP_DS_PORT_TYPE_DP 0
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# define DP_DS_PORT_TYPE_VGA 1
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# define DP_DS_PORT_TYPE_DVI 2
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# define DP_DS_PORT_TYPE_HDMI 3
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# define DP_DS_PORT_TYPE_NON_EDID 4
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# define DP_DS_PORT_HPD (1 << 3)
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/* offset 1 for VGA is maximum megapixels per second / 8 */
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/* offset 2 */
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# define DP_DS_VGA_MAX_BPC_MASK (3 << 0)
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# define DP_DS_VGA_8BPC 0
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# define DP_DS_VGA_10BPC 1
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# define DP_DS_VGA_12BPC 2
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# define DP_DS_VGA_16BPC 3
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/* link configuration */
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#define DP_LINK_BW_SET 0x100
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# define DP_LINK_BW_1_62 0x06
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# define DP_LINK_BW_2_7 0x0a
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# define DP_LINK_BW_5_4 0x14 /* 1.2 */
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#define DP_LANE_COUNT_SET 0x101
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# define DP_LANE_COUNT_MASK 0x0f
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# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
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#define DP_TRAINING_PATTERN_SET 0x102
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# define DP_TRAINING_PATTERN_DISABLE 0
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# define DP_TRAINING_PATTERN_1 1
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# define DP_TRAINING_PATTERN_2 2
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# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
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# define DP_TRAINING_PATTERN_MASK 0x3
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# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
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# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
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# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
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# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
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# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
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# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
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# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
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# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
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# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
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# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
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# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
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#define DP_TRAINING_LANE0_SET 0x103
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#define DP_TRAINING_LANE1_SET 0x104
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#define DP_TRAINING_LANE2_SET 0x105
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#define DP_TRAINING_LANE3_SET 0x106
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# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
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# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
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# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
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# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
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# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
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# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
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#define DP_DOWNSPREAD_CTRL 0x107
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# define DP_SPREAD_AMP_0_5 (1 << 4)
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# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
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#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
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# define DP_SET_ANSI_8B10B (1 << 0)
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#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
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/* bitmask as for DP_I2C_SPEED_CAP */
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#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
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#define DP_MSTM_CTRL 0x111 /* 1.2 */
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# define DP_MST_EN (1 << 0)
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# define DP_UP_REQ_EN (1 << 1)
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# define DP_UPSTREAM_IS_SRC (1 << 2)
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#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
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# define DP_PSR_ENABLE (1 << 0)
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# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
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# define DP_PSR_CRC_VERIFICATION (1 << 2)
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# define DP_PSR_FRAME_CAPTURE (1 << 3)
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#define DP_SINK_COUNT 0x200
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/* prior to 1.2 bit 7 was reserved mbz */
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# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
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# define DP_SINK_CP_READY (1 << 6)
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#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
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# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
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# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
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# define DP_CP_IRQ (1 << 2)
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# define DP_SINK_SPECIFIC_IRQ (1 << 6)
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#define DP_LANE0_1_STATUS 0x202
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#define DP_LANE2_3_STATUS 0x203
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# define DP_LANE_CR_DONE (1 << 0)
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# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
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# define DP_LANE_SYMBOL_LOCKED (1 << 2)
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#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
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DP_LANE_CHANNEL_EQ_DONE | \
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DP_LANE_SYMBOL_LOCKED)
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#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
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#define DP_INTERLANE_ALIGN_DONE (1 << 0)
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#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
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#define DP_LINK_STATUS_UPDATED (1 << 7)
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#define DP_SINK_STATUS 0x205
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#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
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#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
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#define DP_ADJUST_REQUEST_LANE0_1 0x206
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#define DP_ADJUST_REQUEST_LANE2_3 0x207
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# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
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# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
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# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
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# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
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# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
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# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
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# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
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# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
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#define DP_TEST_REQUEST 0x218
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# define DP_TEST_LINK_TRAINING (1 << 0)
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# define DP_TEST_LINK_PATTERN (1 << 1)
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# define DP_TEST_LINK_EDID_READ (1 << 2)
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# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
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#define DP_TEST_LINK_RATE 0x219
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# define DP_LINK_RATE_162 (0x6)
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# define DP_LINK_RATE_27 (0xa)
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#define DP_TEST_LANE_COUNT 0x220
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#define DP_TEST_PATTERN 0x221
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#define DP_TEST_RESPONSE 0x260
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# define DP_TEST_ACK (1 << 0)
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# define DP_TEST_NAK (1 << 1)
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# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
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#define DP_SOURCE_OUI 0x300
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#define DP_SINK_OUI 0x400
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#define DP_BRANCH_OUI 0x500
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#define DP_SET_POWER 0x600
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# define DP_SET_POWER_D0 0x1
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# define DP_SET_POWER_D3 0x2
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#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
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# define DP_PSR_LINK_CRC_ERROR (1 << 0)
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# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
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#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
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# define DP_PSR_CAPS_CHANGE (1 << 0)
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#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
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# define DP_PSR_SINK_INACTIVE 0
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# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
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# define DP_PSR_SINK_ACTIVE_RFB 2
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# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
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# define DP_PSR_SINK_ACTIVE_RESYNC 4
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# define DP_PSR_SINK_INTERNAL_ERROR 7
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# define DP_PSR_SINK_STATE_MASK 0x07
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#define MODE_I2C_START 1
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#define MODE_I2C_WRITE 2
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#define MODE_I2C_READ 4
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#define MODE_I2C_STOP 8
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struct iic_dp_aux_data {
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bool running;
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u16 address;
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void *priv;
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int (*aux_ch)(device_t adapter, int mode, uint8_t write_byte,
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uint8_t *read_byte);
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device_t port;
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};
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int iic_dp_aux_add_bus(device_t dev, const char *name,
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int (*ch)(device_t idev, int mode, uint8_t write_byte, uint8_t *read_byte),
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void *priv, device_t *bus, device_t *adapter);
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#define DP_LINK_STATUS_SIZE 6
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bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count);
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bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count);
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u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane);
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u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane);
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#define DP_RECEIVER_CAP_SIZE 0xf
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void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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u8 drm_dp_link_rate_to_bw_code(int link_rate);
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int drm_dp_bw_code_to_link_rate(u8 link_bw);
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static inline int
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drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])
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{
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return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
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}
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static inline u8
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drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE])
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{
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return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
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}
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#endif /* _DRM_DP_HELPER_H_ */
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