80105e4e72
kernel. Delete it and fix up the 1% difference because there's no need for them to be different.
475 lines
13 KiB
C
475 lines
13 KiB
C
/*
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* Copyright (c) 2003 Hidetoshi Shimokawa
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* Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the acknowledgement as bellow:
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*
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* This product includes software developed by K. Kobayashi and H. Shimokawa
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*
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#include <stand.h>
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#include <btxv86.h>
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#include <bootstrap.h>
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#include <dev/firewire/firewire.h>
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#include "fwohci.h"
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#include <dev/firewire/fwohcireg.h>
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#include <dev/firewire/firewire_phy.h>
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static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t);
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static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t);
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int firewire_debug=0;
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#if 0
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#define device_printf(a, x, ...) printf("FW1394: " x, ## __VA_ARGS__)
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#else
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#define device_printf(a, x, ...)
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#endif
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#define device_t int
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#define DELAY(x) delay(x)
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#define MAX_SPEED 3
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#define MAXREC(x) (2 << (x))
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char *linkspeed[] = {
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"S100", "S200", "S400", "S800",
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"S1600", "S3200", "undef", "undef"
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};
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/*
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* Communication with PHY device
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*/
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static uint32_t
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fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data)
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{
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uint32_t fun;
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addr &= 0xf;
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data &= 0xff;
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fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
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OWRITE(sc, OHCI_PHYACCESS, fun);
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DELAY(100);
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return(fwphy_rddata( sc, addr));
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}
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static uint32_t
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fwphy_rddata(struct fwohci_softc *sc, u_int addr)
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{
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uint32_t fun, stat;
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u_int i, retry = 0;
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addr &= 0xf;
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#define MAX_RETRY 100
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again:
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OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
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fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
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OWRITE(sc, OHCI_PHYACCESS, fun);
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for ( i = 0 ; i < MAX_RETRY ; i ++ ){
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fun = OREAD(sc, OHCI_PHYACCESS);
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if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
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break;
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DELAY(100);
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}
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if(i >= MAX_RETRY) {
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if (firewire_debug)
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device_printf(sc->fc.dev, "phy read failed(1).\n");
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if (++retry < MAX_RETRY) {
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DELAY(100);
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goto again;
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}
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}
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/* Make sure that SCLK is started */
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stat = OREAD(sc, FWOHCI_INTSTAT);
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if ((stat & OHCI_INT_REG_FAIL) != 0 ||
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((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
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if (firewire_debug)
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device_printf(sc->fc.dev, "phy read failed(2).\n");
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if (++retry < MAX_RETRY) {
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DELAY(100);
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goto again;
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}
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}
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if (firewire_debug || retry >= MAX_RETRY)
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device_printf(sc->fc.dev,
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"fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry);
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#undef MAX_RETRY
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return((fun >> PHYDEV_RDDATA )& 0xff);
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}
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static int
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fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
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{
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uint32_t reg, reg2;
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int e1394a = 1;
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int nport, speed;
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/*
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* probe PHY parameters
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* 0. to prove PHY version, whether compliance of 1394a.
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* 1. to probe maximum speed supported by the PHY and
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* number of port supported by core-logic.
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* It is not actually available port on your PC .
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*/
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OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
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DELAY(500);
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reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
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if((reg >> 5) != 7 ){
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nport = reg & FW_PHY_NP;
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speed = reg & FW_PHY_SPD >> 6;
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if (speed > MAX_SPEED) {
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device_printf(dev, "invalid speed %d (fixed to %d).\n",
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speed, MAX_SPEED);
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speed = MAX_SPEED;
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}
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device_printf(dev,
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"Phy 1394 only %s, %d ports.\n",
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linkspeed[speed], nport);
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}else{
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reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
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nport = reg & FW_PHY_NP;
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speed = (reg2 & FW_PHY_ESPD) >> 5;
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if (speed > MAX_SPEED) {
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device_printf(dev, "invalid speed %d (fixed to %d).\n",
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speed, MAX_SPEED);
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speed = MAX_SPEED;
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}
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device_printf(dev,
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"Phy 1394a available %s, %d ports.\n",
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linkspeed[speed], nport);
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/* check programPhyEnable */
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reg2 = fwphy_rddata(sc, 5);
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#if 0
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if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
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#else /* XXX force to enable 1394a */
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if (e1394a) {
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#endif
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if (firewire_debug)
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device_printf(dev,
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"Enable 1394a Enhancements\n");
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/* enable EAA EMC */
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reg2 |= 0x03;
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/* set aPhyEnhanceEnable */
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OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
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OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
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} else {
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/* for safe */
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reg2 &= ~0x83;
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}
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reg2 = fwphy_wrdata(sc, 5, reg2);
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}
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sc->speed = speed;
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reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
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if((reg >> 5) == 7 ){
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reg = fwphy_rddata(sc, 4);
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reg |= 1 << 6;
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fwphy_wrdata(sc, 4, reg);
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reg = fwphy_rddata(sc, 4);
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}
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return 0;
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}
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void
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fwohci_reset(struct fwohci_softc *sc, device_t dev)
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{
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int i, max_rec, speed;
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uint32_t reg, reg2;
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/* Disable interrupts */
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OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
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/* FLUSH FIFO and reset Transmitter/Receiver */
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OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
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if (firewire_debug)
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device_printf(dev, "resetting OHCI...");
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i = 0;
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while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
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if (i++ > 100) break;
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DELAY(1000);
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}
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if (firewire_debug)
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printf("done (loop=%d)\n", i);
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/* Probe phy */
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fwohci_probe_phy(sc, dev);
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/* Probe link */
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reg = OREAD(sc, OHCI_BUS_OPT);
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reg2 = reg | OHCI_BUSFNC;
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max_rec = (reg & 0x0000f000) >> 12;
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speed = (reg & 0x00000007);
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device_printf(dev, "Link %s, max_rec %d bytes.\n",
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linkspeed[speed], MAXREC(max_rec));
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/* XXX fix max_rec */
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sc->maxrec = sc->speed + 8;
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if (max_rec != sc->maxrec) {
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reg2 = (reg2 & 0xffff0fff) | (sc->maxrec << 12);
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device_printf(dev, "max_rec %d -> %d\n",
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MAXREC(max_rec), MAXREC(sc->maxrec));
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}
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if (firewire_debug)
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device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
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OWRITE(sc, OHCI_BUS_OPT, reg2);
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/* Initialize registers */
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OWRITE(sc, OHCI_CROMHDR, sc->config_rom[0]);
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OWRITE(sc, OHCI_CROMPTR, VTOP(sc->config_rom));
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#if 0
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OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
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#endif
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OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
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OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
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#if 0
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OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
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#endif
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/* Enable link */
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OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
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}
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int
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fwohci_init(struct fwohci_softc *sc, device_t dev)
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{
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int i, mver;
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uint32_t reg;
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uint8_t ui[8];
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/* OHCI version */
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reg = OREAD(sc, OHCI_VERSION);
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mver = (reg >> 16) & 0xff;
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device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
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mver, reg & 0xff, (reg>>24) & 1);
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if (mver < 1 || mver > 9) {
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device_printf(dev, "invalid OHCI version\n");
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return (ENXIO);
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}
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/* Available Isochronous DMA channel probe */
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OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
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OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
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reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
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OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
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OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
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for (i = 0; i < 0x20; i++)
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if ((reg & (1 << i)) == 0)
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break;
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device_printf(dev, "No. of Isochronous channels is %d.\n", i);
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if (i == 0)
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return (ENXIO);
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#if 0
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/* SID receive buffer must align 2^11 */
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#define OHCI_SIDSIZE (1 << 11)
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sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
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&sc->sid_dma, BUS_DMA_WAITOK);
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if (sc->sid_buf == NULL) {
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device_printf(dev, "sid_buf alloc failed.");
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return ENOMEM;
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}
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#endif
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sc->eui.hi = OREAD(sc, FWOHCIGUID_H);
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sc->eui.lo = OREAD(sc, FWOHCIGUID_L);
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for( i = 0 ; i < 8 ; i ++)
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ui[i] = FW_EUI64_BYTE(&sc->eui,i);
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device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
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ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
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fwohci_reset(sc, dev);
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return 0;
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}
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void
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fwohci_ibr(struct fwohci_softc *sc)
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{
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uint32_t fun;
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device_printf(sc->dev, "Initiate bus reset\n");
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/*
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* Make sure our cached values from the config rom are
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* initialised.
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*/
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OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0]));
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OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2]));
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/*
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* Set root hold-off bit so that non cyclemaster capable node
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* shouldn't became the root node.
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*/
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#if 1
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fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
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fun |= FW_PHY_IBR;
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fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
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#else /* Short bus reset */
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fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
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fun |= FW_PHY_ISBR;
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fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
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#endif
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}
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void
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fwohci_sid(struct fwohci_softc *sc)
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{
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uint32_t node_id;
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int plen;
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node_id = OREAD(sc, FWOHCI_NODEID);
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if (!(node_id & OHCI_NODE_VALID)) {
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#if 0
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printf("Bus reset failure\n");
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#endif
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return;
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}
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/* Enable bus reset interrupt */
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OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
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/* Allow async. request to us */
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OWRITE(sc, OHCI_AREQHI, 1 << 31);
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/* XXX insecure ?? */
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OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
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OWRITE(sc, OHCI_PREQLO, 0xffffffff);
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OWRITE(sc, OHCI_PREQUPPER, 0x10000);
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/* Set ATRetries register */
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OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
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/*
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** Checking whether the node is root or not. If root, turn on
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** cycle master.
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*/
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plen = OREAD(sc, OHCI_SID_CNT);
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device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
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node_id, (plen >> 16) & 0xff);
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if (node_id & OHCI_NODE_ROOT) {
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device_printf(sc->dev, "CYCLEMASTER mode\n");
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OWRITE(sc, OHCI_LNKCTL,
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OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
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} else {
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device_printf(sc->dev, "non CYCLEMASTER mode\n");
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OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
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OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
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}
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if (plen & OHCI_SID_ERR) {
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device_printf(fc->dev, "SID Error\n");
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return;
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}
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device_printf(sc->dev, "bus reset phase done\n");
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sc->state = FWOHCI_STATE_NORMAL;
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}
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static void
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fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count)
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{
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#undef OHCI_DEBUG
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#ifdef OHCI_DEBUG
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#if 0
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if(stat & OREAD(sc, FWOHCI_INTMASK))
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#else
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if (1)
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#endif
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device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
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stat & OHCI_INT_EN ? "DMA_EN ":"",
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stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
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stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
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stat & OHCI_INT_ERR ? "INT_ERR ":"",
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stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
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stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
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stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
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stat & OHCI_INT_CYC_START ? "CYC_START ":"",
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stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
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stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
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stat & OHCI_INT_PHY_SID ? "SID ":"",
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stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
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stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
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stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
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stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
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stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
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stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
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stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
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stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
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stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
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stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
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stat, OREAD(sc, FWOHCI_INTMASK)
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);
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#endif
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/* Bus reset */
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if(stat & OHCI_INT_PHY_BUS_R ){
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device_printf(fc->dev, "BUS reset\n");
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if (sc->state == FWOHCI_STATE_BUSRESET)
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goto busresetout;
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sc->state = FWOHCI_STATE_BUSRESET;
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/* Disable bus reset interrupt until sid recv. */
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OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
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OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
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OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
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OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0]));
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OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2]));
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} else if (sc->state == FWOHCI_STATE_BUSRESET) {
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fwohci_sid(sc);
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}
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busresetout:
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return;
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}
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static uint32_t
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fwochi_check_stat(struct fwohci_softc *sc)
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|
{
|
|
uint32_t stat;
|
|
|
|
stat = OREAD(sc, FWOHCI_INTSTAT);
|
|
if (stat == 0xffffffff) {
|
|
device_printf(sc->fc.dev,
|
|
"device physically ejected?\n");
|
|
return(stat);
|
|
}
|
|
if (stat)
|
|
OWRITE(sc, FWOHCI_INTSTATCLR, stat);
|
|
return(stat);
|
|
}
|
|
|
|
void
|
|
fwohci_poll(struct fwohci_softc *sc)
|
|
{
|
|
uint32_t stat;
|
|
|
|
stat = fwochi_check_stat(sc);
|
|
if (stat != 0xffffffff)
|
|
fwohci_intr_body(sc, stat, 1);
|
|
}
|