a1b4155638
PCPU fields for curthread, by doing the same to Book-E. This closes some potential races switching between CPUs. As a side effect, it turns out the AIM and Book-E swtch.S implementations were the same to within a few registers, so move that to powerpc/powerpc. MFC after: 3 months
91 lines
2.5 KiB
C
91 lines
2.5 KiB
C
/*-
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* Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/smp.h>
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#include <machine/pcb.h>
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#include <machine/psl.h>
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#include <machine/smp.h>
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#include <machine/spr.h>
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extern void dcache_enable(void);
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extern void dcache_inval(void);
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extern void icache_enable(void);
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extern void icache_inval(void);
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volatile void *ap_pcpu;
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uintptr_t
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cpudep_ap_bootstrap()
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{
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uint32_t msr, sp, csr;
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/* Enable L1 caches */
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csr = mfspr(SPR_L1CSR0);
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if ((csr & L1CSR0_DCE) == 0) {
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dcache_inval();
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dcache_enable();
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}
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csr = mfspr(SPR_L1CSR1);
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if ((csr & L1CSR1_ICE) == 0) {
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icache_inval();
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icache_enable();
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}
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/* Set MSR */
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msr = PSL_ME;
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mtmsr(msr);
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/* Assign pcpu fields, return ptr to this AP's idle thread kstack */
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pcpup->pc_curthread = pcpup->pc_idlethread;
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#ifdef __powerpc64__
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__asm __volatile("mr 13,%0" :: "r"(pcpup->pc_curthread));
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#else
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__asm __volatile("mr 2,%0" :: "r"(pcpup->pc_curthread));
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#endif
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pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
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sp = pcpup->pc_curpcb->pcb_sp;
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/* XXX shouldn't the pcb_sp be checked/forced for alignment here?? */
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return (sp);
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}
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void
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cpudep_ap_setup()
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{
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}
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