e948693ed7
based on Solarflare SFC9000 family controllers. The driver supports jumbo frames, transmit/receive checksum offload, TCP Segmentation Offload (TSO), Large Receive Offload (LRO), VLAN checksum offload, VLAN TSO, and Receive Side Scaling (RSS) using MSI-X interrupts. This work was sponsored by Solarflare Communications, Inc. My sincere thanks to Ben Hutchings for doing a lot of the hard work! Sponsored by: Solarflare Communications, Inc. MFC after: 3 weeks
431 lines
11 KiB
C
431 lines
11 KiB
C
/*-
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* Copyright 2007-2009 Solarflare Communications Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "efsys.h"
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#include "efx.h"
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#include "efx_types.h"
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#include "efx_regs.h"
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#include "efx_impl.h"
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#if EFSYS_OPT_QSTATS
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#define EFX_TX_QSTAT_INCR(_etp, _stat) \
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do { \
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(_etp)->et_stat[_stat]++; \
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_NOTE(CONSTANTCONDITION) \
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} while (B_FALSE)
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#else
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#define EFX_TX_QSTAT_INCR(_etp, _stat)
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#endif
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__checkReturn int
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efx_tx_init(
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__in efx_nic_t *enp)
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{
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efx_oword_t oword;
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int rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
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if (!(enp->en_mod_flags & EFX_MOD_EV)) {
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rc = EINVAL;
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goto fail1;
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}
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if (enp->en_mod_flags & EFX_MOD_TX) {
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rc = EINVAL;
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goto fail2;
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}
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EFSYS_ASSERT3U(enp->en_tx_qcount, ==, 0);
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/*
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* Disable the timer-based TX DMA backoff and allow TX DMA to be
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* controlled by the RX FIFO fill level (although always allow a
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* minimal trickle).
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*/
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EFX_BAR_READO(enp, FR_AZ_TX_RESERVED_REG, &oword);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_RX_SPACER, 0xfe);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_RX_SPACER_EN, 1);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_PUSH_EN, 0);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DIS_NON_IP_EV, 1);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_PREF_THRESHOLD, 2);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
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/*
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* Filter all packets less than 14 bytes to avoid parsing
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* errors.
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*/
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EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
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EFX_BAR_WRITEO(enp, FR_AZ_TX_RESERVED_REG, &oword);
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/*
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* Do not set TX_NO_EOP_DISC_EN, since it limits packets to 16
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* descriptors (which is bad).
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*/
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EFX_BAR_READO(enp, FR_AZ_TX_CFG_REG, &oword);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
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EFX_BAR_WRITEO(enp, FR_AZ_TX_CFG_REG, &oword);
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enp->en_mod_flags |= EFX_MOD_TX;
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return (0);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, int, rc);
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return (rc);
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}
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#if EFSYS_OPT_FILTER
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extern __checkReturn int
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efx_tx_filter_insert(
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__in efx_txq_t *etp,
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__inout efx_filter_spec_t *spec)
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{
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EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
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EFSYS_ASSERT3P(spec, !=, NULL);
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spec->efs_dmaq_id = (uint16_t)etp->et_index;
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return efx_filter_insert_filter(etp->et_enp, spec, B_FALSE);
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}
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#endif
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#if EFSYS_OPT_FILTER
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extern __checkReturn int
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efx_tx_filter_remove(
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__in efx_txq_t *etp,
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__inout efx_filter_spec_t *spec)
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{
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EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
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EFSYS_ASSERT3P(spec, !=, NULL);
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spec->efs_dmaq_id = (uint16_t)etp->et_index;
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return efx_filter_remove_filter(etp->et_enp, spec);
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}
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#endif
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#define EFX_TX_DESC(_etp, _addr, _size, _eop, _added) \
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do { \
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unsigned int id; \
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size_t offset; \
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efx_qword_t qword; \
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\
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id = (_added)++ & (_etp)->et_mask; \
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offset = id * sizeof (efx_qword_t); \
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\
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EFSYS_PROBE5(tx_post, unsigned int, (_etp)->et_index, \
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unsigned int, id, efsys_dma_addr_t, (_addr), \
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size_t, (_size), boolean_t, (_eop)); \
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\
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EFX_POPULATE_QWORD_4(qword, \
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FSF_AZ_TX_KER_CONT, (_eop) ? 0 : 1, \
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FSF_AZ_TX_KER_BYTE_COUNT, (uint32_t)(_size), \
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FSF_AZ_TX_KER_BUF_ADDR_DW0, \
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(uint32_t)((_addr) & 0xffffffff), \
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FSF_AZ_TX_KER_BUF_ADDR_DW1, \
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(uint32_t)((_addr) >> 32)); \
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EFSYS_MEM_WRITEQ((_etp)->et_esmp, offset, &qword); \
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\
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_NOTE(CONSTANTCONDITION) \
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} while (B_FALSE)
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__checkReturn int
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efx_tx_qpost(
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__in efx_txq_t *etp,
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__in_ecount(n) efx_buffer_t *eb,
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__in unsigned int n,
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__in unsigned int completed,
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__inout unsigned int *addedp)
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{
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unsigned int added = *addedp;
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unsigned int i;
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int rc = ENOSPC;
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EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
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if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1))
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goto fail1;
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for (i = 0; i < n; i++) {
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efx_buffer_t *ebp = &eb[i];
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efsys_dma_addr_t start = ebp->eb_addr;
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size_t size = ebp->eb_size;
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efsys_dma_addr_t end = start + size;
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/* Fragments must not span 4k boundaries. */
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EFSYS_ASSERT(P2ROUNDUP(start + 1, 4096) >= end);
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EFX_TX_DESC(etp, start, size, ebp->eb_eop, added);
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}
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EFX_TX_QSTAT_INCR(etp, TX_POST);
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*addedp = added;
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return (0);
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fail1:
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EFSYS_PROBE1(fail1, int, rc);
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return (rc);
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}
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void
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efx_tx_qpush(
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__in efx_txq_t *etp,
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__in unsigned int added)
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{
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efx_nic_t *enp = etp->et_enp;
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uint32_t wptr;
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efx_dword_t dword;
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efx_oword_t oword;
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EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
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/* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
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EFSYS_PIO_WRITE_BARRIER();
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/* Push the populated descriptors out */
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wptr = added & etp->et_mask;
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DESC_WPTR, wptr);
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/* Only write the third DWORD */
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EFX_POPULATE_DWORD_1(dword,
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EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
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EFX_BAR_TBL_WRITED3(enp, FR_BZ_TX_DESC_UPD_REGP0,
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etp->et_index, &dword, B_FALSE);
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}
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void
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efx_tx_qflush(
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__in efx_txq_t *etp)
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{
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efx_nic_t *enp = etp->et_enp;
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efx_oword_t oword;
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uint32_t label;
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EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
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label = etp->et_index;
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/* Flush the queue */
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EFX_POPULATE_OWORD_2(oword, FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
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FRF_AZ_TX_FLUSH_DESCQ, label);
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EFX_BAR_WRITEO(enp, FR_AZ_TX_FLUSH_DESCQ_REG, &oword);
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}
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void
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efx_tx_qenable(
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__in efx_txq_t *etp)
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{
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efx_nic_t *enp = etp->et_enp;
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efx_oword_t oword;
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EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
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EFX_BAR_TBL_READO(enp, FR_AZ_TX_DESC_PTR_TBL,
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etp->et_index, &oword);
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EFSYS_PROBE5(tx_descq_ptr, unsigned int, etp->et_index,
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uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_3),
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uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_2),
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uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_1),
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uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_0));
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DC_HW_RPTR, 0);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DESCQ_HW_RPTR, 0);
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EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DESCQ_EN, 1);
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EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_DESC_PTR_TBL,
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etp->et_index, &oword);
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}
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__checkReturn int
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efx_tx_qcreate(
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__in efx_nic_t *enp,
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__in unsigned int index,
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__in unsigned int label,
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__in efsys_mem_t *esmp,
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__in size_t n,
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__in uint32_t id,
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__in uint16_t flags,
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__in efx_evq_t *eep,
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__deref_out efx_txq_t **etpp)
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{
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efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
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efx_txq_t *etp;
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efx_oword_t oword;
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uint32_t size;
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int rc;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_TX);
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EFX_STATIC_ASSERT(EFX_EV_TX_NLABELS == (1 << FRF_AZ_TX_DESCQ_LABEL_WIDTH));
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EFSYS_ASSERT3U(label, <, EFX_EV_TX_NLABELS);
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EFSYS_ASSERT3U(enp->en_tx_qcount + 1, <, encp->enc_txq_limit);
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if (!ISP2(n) || !(n & EFX_TXQ_NDESCS_MASK)) {
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rc = EINVAL;
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goto fail1;
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}
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if (index >= encp->enc_txq_limit) {
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rc = EINVAL;
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goto fail2;
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}
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for (size = 0; (1 << size) <= (EFX_TXQ_MAXNDESCS / EFX_TXQ_MINNDESCS);
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size++)
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if ((1 << size) == (int)(n / EFX_TXQ_MINNDESCS))
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break;
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if (id + (1 << size) >= encp->enc_buftbl_limit) {
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rc = EINVAL;
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goto fail3;
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}
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/* Allocate an TXQ object */
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EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_txq_t), etp);
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if (etp == NULL) {
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rc = ENOMEM;
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goto fail4;
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}
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etp->et_magic = EFX_TXQ_MAGIC;
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etp->et_enp = enp;
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etp->et_index = index;
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etp->et_mask = n - 1;
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etp->et_esmp = esmp;
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/* Set up the new descriptor queue */
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EFX_POPULATE_OWORD_6(oword,
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FRF_AZ_TX_DESCQ_BUF_BASE_ID, id,
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FRF_AZ_TX_DESCQ_EVQ_ID, eep->ee_index,
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FRF_AZ_TX_DESCQ_OWNER_ID, 0,
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FRF_AZ_TX_DESCQ_LABEL, label,
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FRF_AZ_TX_DESCQ_SIZE, size,
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FRF_AZ_TX_DESCQ_TYPE, 0);
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EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_NON_IP_DROP_DIS, 1);
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EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_IP_CHKSM_DIS,
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(flags & EFX_CKSUM_IPV4) ? 0 : 1);
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EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_TCP_CHKSM_DIS,
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(flags & EFX_CKSUM_TCPUDP) ? 0 : 1);
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EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_DESC_PTR_TBL,
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etp->et_index, &oword);
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enp->en_tx_qcount++;
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*etpp = etp;
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return (0);
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fail4:
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EFSYS_PROBE(fail4);
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fail3:
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EFSYS_PROBE(fail3);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, int, rc);
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return (rc);
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}
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#if EFSYS_OPT_NAMES
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/* START MKCONFIG GENERATED EfxTransmitQueueStatNamesBlock 78ca9ab00287fffb */
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static const char __cs * __cs __efx_tx_qstat_name[] = {
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"post",
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"unaligned_split",
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};
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/* END MKCONFIG GENERATED EfxTransmitQueueStatNamesBlock */
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const char __cs *
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efx_tx_qstat_name(
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__in efx_nic_t *enp,
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__in unsigned int id)
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{
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_NOTE(ARGUNUSED(enp))
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(id, <, TX_NQSTATS);
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return (__efx_tx_qstat_name[id]);
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}
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#endif /* EFSYS_OPT_NAMES */
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#if EFSYS_OPT_QSTATS
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void
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efx_tx_qstats_update(
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__in efx_txq_t *etp,
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__inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
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{
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unsigned int id;
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EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
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for (id = 0; id < TX_NQSTATS; id++) {
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efsys_stat_t *essp = &stat[id];
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EFSYS_STAT_INCR(essp, etp->et_stat[id]);
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etp->et_stat[id] = 0;
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}
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}
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#endif /* EFSYS_OPT_QSTATS */
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void
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efx_tx_qdestroy(
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__in efx_txq_t *etp)
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{
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efx_nic_t *enp = etp->et_enp;
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efx_oword_t oword;
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EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
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EFSYS_ASSERT(enp->en_tx_qcount != 0);
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--enp->en_tx_qcount;
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/* Purge descriptor queue */
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EFX_ZERO_OWORD(oword);
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EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_DESC_PTR_TBL,
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etp->et_index, &oword);
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/* Free the TXQ object */
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EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_txq_t), etp);
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}
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void
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efx_tx_fini(
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__in efx_nic_t *enp)
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{
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
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EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_TX);
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EFSYS_ASSERT3U(enp->en_tx_qcount, ==, 0);
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enp->en_mod_flags &= ~EFX_MOD_TX;
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}
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