e911eafcba
CLBYTES PD_SHIFT PGSHIFT NBPG PGOFSET CLSIZELOG2 CLSIZE pdei()
ptei() kvtopte() ptetov() ispt() ptetoav() &c &c
new:
NPDEPG
Major macro cleanup.
308 lines
7.0 KiB
C
308 lines
7.0 KiB
C
/*
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* Copyright 1996 Massachusetts Institute of Technology
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*
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby
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* granted, provided that both the above copyright notice and this
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* permission notice appear in all copies, that both the above
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* copyright notice and this permission notice appear in all
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* supporting documentation, and that the name of M.I.T. not be used
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* in advertising or publicity pertaining to distribution of the
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* software without specific, written prior permission. M.I.T. makes
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* no representations about the suitability of this software for any
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* purpose. It is provided "as is" without express or implied
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* warranty.
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*
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* THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
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* ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
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* SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: wd82371.c,v 1.3 1996/04/07 17:39:17 bde Exp $
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*/
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#include "pci.h"
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#if NPCI > 0
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/queue.h>
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#include <sys/proc.h>
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#include <sys/buf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/pmap.h> /* for vtophys */
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#include <i386/isa/wdreg.h>
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#include <pci/pcivar.h>
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#include <pci/pcireg.h>
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#include <pci/wd82371reg.h>
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static void *piix_candma(int, int);
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static int piix_dmasetup(void *, char *, u_long, int);
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static void piix_dmastart(void *);
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static int piix_dmadone(void *);
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static int piix_status(void *);
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struct piix_cookie {
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LIST_ENTRY(piix_cookie) le;
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int ctlr;
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int unit;
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struct piix_prd *prd;
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};
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struct piix_softc {
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unsigned iobase;
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pcici_t tag;
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LIST_HEAD(, piix_cookie) cookies;
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};
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static struct piix_softc softc;
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static struct piix_cookie *
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mkcookie(int ctlr, int unit)
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{
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struct piix_cookie *cp;
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cp = malloc(sizeof *cp, M_DEVBUF, M_NOWAIT);
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if (!cp) return cp;
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cp->ctlr = ctlr;
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cp->unit = unit;
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cp->prd = malloc(PRD_ALLOC_SIZE, M_DEVBUF, M_NOWAIT);
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if (!cp->prd) {
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FREE(cp, M_DEVBUF);
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return 0;
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}
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LIST_INSERT_HEAD(&softc.cookies, cp, le);
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return cp;
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}
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static char *
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piix_probe(pcici_t tag, pcidi_t type)
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{
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if (type == 0x12308086)
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return ("Intel 82371 (Triton) Bus-master IDE controller");
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return 0;
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}
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static void
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piix_attach(pcici_t tag, int unit)
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{
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u_long idetm;
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int bmista;
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int iobase;
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if (unit) return;
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softc.tag = tag;
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iobase = softc.iobase = pci_conf_read(tag, 0x20) & 0xfff0;
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idetm = pci_conf_read(tag, 0x40);
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LIST_INIT(&softc.cookies);
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if (IDETM_CTLR_0(idetm) & IDETM_ENABLE) {
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bmista = inb(iobase + BMISTA_PORT);
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if (bmista & BMISTA_DMA0CAP)
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mkcookie(0, 0);
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if (bmista & BMISTA_DMA1CAP)
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mkcookie(0, 1);
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}
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if (IDETM_CTLR_1(idetm) & IDETM_ENABLE) {
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bmista = inb(iobase + PIIX_CTLR_1 + BMISTA_PORT);
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if (bmista & BMISTA_DMA0CAP)
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mkcookie(1, 0);
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if (bmista & BMISTA_DMA1CAP)
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mkcookie(1, 1);
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}
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wddma.wdd_candma = piix_candma;
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wddma.wdd_dmaprep = piix_dmasetup;
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wddma.wdd_dmastart = piix_dmastart;
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wddma.wdd_dmadone = piix_dmadone;
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wddma.wdd_dmastatus = piix_status;
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}
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static u_long piix_count;
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static struct pci_device piix_device = {
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"piix",
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piix_probe,
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piix_attach,
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&piix_count,
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0
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};
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DATA_SET(pcidevice_set, piix_device);
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/*
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* Return a cookie if we can do DMA on the specified (ctlr, unit).
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*/
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static void *
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piix_candma(int ctlr, int unit)
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{
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struct piix_cookie *cp;
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cp = softc.cookies.lh_first;
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while(cp) {
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if (cp->unit == unit && cp->ctlr == ctlr)
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break;
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cp = cp->le.le_next;
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}
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return cp;
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}
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/*
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* Set up DMA for cp. It is the responsibility of the caller
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* to ensure that the controller is idle before this routine
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* is called.
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*/
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static int
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piix_dmasetup(void *xcp, char *vaddr, u_long count, int dir)
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{
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struct piix_cookie *cp = xcp;
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struct piix_prd *prd;
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int i;
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u_long pgresid;
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int iobase;
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prd = cp->prd;
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i = 0;
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iobase = softc.iobase + cp->ctlr ? PIIX_CTLR_1 : 0;
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/*
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* Deal with transfers that don't start on a page
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* boundary.
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*/
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pgresid = (u_long)vaddr % PAGE_SIZE;
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if (pgresid) {
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prd[i].prd_base = vtophys(vaddr);
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if (count >= (PAGE_SIZE - pgresid))
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prd[i].prd_count = PAGE_SIZE - pgresid;
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else
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prd[i].prd_count = count;
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vaddr += prd[i].prd_count;
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count -= prd[i].prd_count;
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prd[i].prd_eot |= PRD_EOT_BIT;
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i++;
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}
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/*
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* We have now ensured that vaddr is page-aligned, so just
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* step through the pages adding each one onto the list.
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*/
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while(count) {
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u_long phys, n;
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phys = vtophys(vaddr);
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n = (count > PAGE_SIZE) ? PAGE_SIZE : count;
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/*
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* If the current page is physically contiguous with
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* whatever we have in the previous PRD, just tack it
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* onto the end.
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* CAVEAT: due to a hardware deficiency, PRDs
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* cannot cross a 64K boundary.
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*/
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if (i > 0
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&& phys == prd[i - 1].prd_base + prd[i - 1].prd_count
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&& ((prd[i - 1].prd_base & 0xffff)
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+ prd[i - 1].prd_count + n) <= 65535) {
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prd[i - 1].prd_count += n;
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} else {
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if (i > 0)
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prd[i - 1].prd_eot &= ~PRD_EOT_BIT;
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prd[i].prd_base = phys;
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prd[i].prd_count = n;
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prd[i].prd_eot |= PRD_EOT_BIT;
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i++;
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if (i >= PRD_MAX_SEGS)
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panic("wd82371: too many segments\n");
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}
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count -= n;
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vaddr += n;
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}
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/* Set up PRD base register */
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outl(iobase + BMIDTP_PORT, vtophys(prd));
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/* Set direction of transfer */
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if (dir == B_READ) {
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outb(iobase + BMICOM_PORT, 0);
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} else {
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outb(iobase + BMICOM_PORT, BMICOM_READ_WRITE);
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}
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/* Clear interrupt and error bits */
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outb(iobase + BMISTA_PORT,
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(inb(iobase + BMISTA_PORT)
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& ~(BMISTA_INTERRUPT | BMISTA_DMA_ERROR)));
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return 0;
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}
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static void
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piix_dmastart(void *xcp)
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{
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struct piix_cookie *cp = xcp;
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int iobase;
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iobase = softc.iobase + cp->ctlr ? PIIX_CTLR_1 : 0;
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outb(iobase + BMICOM_PORT,
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inb(iobase + BMICOM_PORT) | BMICOM_STOP_START);
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}
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static int
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piix_dmadone(void *xcp)
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{
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struct piix_cookie *cp = xcp;
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int iobase, status;
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status = piix_status(xcp);
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iobase = softc.iobase + cp->ctlr ? PIIX_CTLR_1 : 0;
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outb(iobase + BMICOM_PORT,
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inb(iobase + BMICOM_PORT) & ~BMICOM_STOP_START);
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return status;
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}
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static int
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piix_status(void *xcp)
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{
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struct piix_cookie *cp = xcp;
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int iobase, status, bmista;
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status = 0;
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iobase = softc.iobase + cp->ctlr ? PIIX_CTLR_1 : 0;
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bmista = inb(iobase + BMISTA_PORT);
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if (bmista & BMISTA_INTERRUPT)
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status |= WDDS_INTERRUPT;
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if (bmista & BMISTA_DMA_ERROR)
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status |= WDDS_ERROR;
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if (bmista & BMISTA_DMA_ACTIVE)
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status |= WDDS_ACTIVE;
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return status;
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}
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#endif /* NPCI > 0 */
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