10d0cdfc6e
The POWER9 MMU (PowerISA 3.0) is slightly different from current configurations, using a partition table even for hypervisor mode, and dropping the SDR1 register. Key off the newly early-enabled CPU features flags for the new architecture, and configure the MMU appropriately. The POWER9 MMU ignores the "PSIZ" field in the PTCR, and expects a 64kB table. As we are enabled for powernv (hypervisor mode, no VMs), only initialize partition table entry 0, and zero out the rest. The actual contents of the register are identical to SDR1 from previous architectures. Along with this, fix a bug in the page table allocation with very large memory. The table can be allocated on any 256k boundary. The bootstrap_alloc alignment argument is an int, and with large amounts of memory passing the size of the table as the alignment will overflow an integer. Hard-code the alignment at 256k as wider alignment is not necessary. Reviewed by: nwhitehorn Tested by: Breno Leitao Relnotes: Yes |
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| .. | ||
| aim_machdep.c | ||
| locore32.S | ||
| locore64.S | ||
| locore.S | ||
| mmu_oea64.c | ||
| mmu_oea64.h | ||
| mmu_oea.c | ||
| moea64_if.m | ||
| moea64_native.c | ||
| mp_cpudep.c | ||
| slb.c | ||
| trap_subr32.S | ||
| trap_subr64.S | ||