66f71b7d24
decode. This is to accomodate hardware assist implementations that do not provide the 'guest linear address' as part of nested page fault collateral. Submitted by: Anish Gupta (akgupt3 at gmail dot com)
868 lines
18 KiB
C
868 lines
18 KiB
C
/*-
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* Copyright (c) 2012 Sandvine, Inc.
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* Copyright (c) 2012 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#ifdef _KERNEL
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#include <sys/param.h>
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#include <sys/pcpu.h>
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#include <sys/systm.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/pmap.h>
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#include <machine/vmparam.h>
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#include <machine/vmm.h>
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#else /* !_KERNEL */
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#include <sys/types.h>
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#include <sys/errno.h>
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#include <machine/vmm.h>
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#include <vmmapi.h>
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#endif /* _KERNEL */
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/* struct vie_op.op_type */
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enum {
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VIE_OP_TYPE_NONE = 0,
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VIE_OP_TYPE_MOV,
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VIE_OP_TYPE_AND,
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VIE_OP_TYPE_LAST
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};
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/* struct vie_op.op_flags */
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#define VIE_OP_F_IMM (1 << 0) /* immediate operand present */
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#define VIE_OP_F_IMM8 (1 << 1) /* 8-bit immediate operand */
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static const struct vie_op one_byte_opcodes[256] = {
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[0x88] = {
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.op_byte = 0x88,
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.op_type = VIE_OP_TYPE_MOV,
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},
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[0x89] = {
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.op_byte = 0x89,
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.op_type = VIE_OP_TYPE_MOV,
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},
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[0x8B] = {
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.op_byte = 0x8B,
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.op_type = VIE_OP_TYPE_MOV,
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},
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[0xC7] = {
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.op_byte = 0xC7,
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.op_type = VIE_OP_TYPE_MOV,
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.op_flags = VIE_OP_F_IMM,
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},
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[0x23] = {
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.op_byte = 0x23,
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.op_type = VIE_OP_TYPE_AND,
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},
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[0x81] = {
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/* XXX Group 1 extended opcode - not just AND */
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.op_byte = 0x81,
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.op_type = VIE_OP_TYPE_AND,
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.op_flags = VIE_OP_F_IMM,
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}
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};
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/* struct vie.mod */
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#define VIE_MOD_INDIRECT 0
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#define VIE_MOD_INDIRECT_DISP8 1
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#define VIE_MOD_INDIRECT_DISP32 2
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#define VIE_MOD_DIRECT 3
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/* struct vie.rm */
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#define VIE_RM_SIB 4
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#define VIE_RM_DISP32 5
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#define GB (1024 * 1024 * 1024)
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static enum vm_reg_name gpr_map[16] = {
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VM_REG_GUEST_RAX,
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VM_REG_GUEST_RCX,
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VM_REG_GUEST_RDX,
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VM_REG_GUEST_RBX,
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VM_REG_GUEST_RSP,
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VM_REG_GUEST_RBP,
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VM_REG_GUEST_RSI,
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VM_REG_GUEST_RDI,
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VM_REG_GUEST_R8,
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VM_REG_GUEST_R9,
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VM_REG_GUEST_R10,
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VM_REG_GUEST_R11,
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VM_REG_GUEST_R12,
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VM_REG_GUEST_R13,
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VM_REG_GUEST_R14,
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VM_REG_GUEST_R15
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};
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static uint64_t size2mask[] = {
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[1] = 0xff,
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[2] = 0xffff,
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[4] = 0xffffffff,
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[8] = 0xffffffffffffffff,
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};
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static int
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vie_valid_register(enum vm_reg_name reg)
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{
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#ifdef _KERNEL
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/*
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* XXX
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* The operand register in which we store the result of the
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* read must be a GPR that we can modify even if the vcpu
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* is "running". All the GPRs qualify except for %rsp.
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*
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* This is a limitation of the vm_set_register() API
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* and can be fixed if necessary.
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*/
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if (reg == VM_REG_GUEST_RSP)
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return (0);
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#endif
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return (1);
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}
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static int
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vie_read_register(void *vm, int vcpuid, enum vm_reg_name reg, uint64_t *rval)
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{
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int error;
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if (!vie_valid_register(reg))
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return (EINVAL);
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error = vm_get_register(vm, vcpuid, reg, rval);
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return (error);
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}
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static int
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vie_read_bytereg(void *vm, int vcpuid, struct vie *vie, uint8_t *rval)
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{
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uint64_t val;
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int error, rshift;
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enum vm_reg_name reg;
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rshift = 0;
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reg = gpr_map[vie->reg];
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/*
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* 64-bit mode imposes limitations on accessing legacy byte registers.
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*
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* The legacy high-byte registers cannot be addressed if the REX
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* prefix is present. In this case the values 4, 5, 6 and 7 of the
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* 'ModRM:reg' field address %spl, %bpl, %sil and %dil respectively.
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*
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* If the REX prefix is not present then the values 4, 5, 6 and 7
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* of the 'ModRM:reg' field address the legacy high-byte registers,
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* %ah, %ch, %dh and %bh respectively.
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*/
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if (!vie->rex_present) {
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if (vie->reg & 0x4) {
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/*
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* Obtain the value of %ah by reading %rax and shifting
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* right by 8 bits (same for %bh, %ch and %dh).
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*/
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rshift = 8;
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reg = gpr_map[vie->reg & 0x3];
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}
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}
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if (!vie_valid_register(reg))
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return (EINVAL);
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error = vm_get_register(vm, vcpuid, reg, &val);
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*rval = val >> rshift;
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return (error);
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}
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static int
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vie_update_register(void *vm, int vcpuid, enum vm_reg_name reg,
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uint64_t val, int size)
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{
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int error;
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uint64_t origval;
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if (!vie_valid_register(reg))
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return (EINVAL);
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switch (size) {
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case 1:
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case 2:
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error = vie_read_register(vm, vcpuid, reg, &origval);
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if (error)
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return (error);
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val &= size2mask[size];
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val |= origval & ~size2mask[size];
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break;
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case 4:
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val &= 0xffffffffUL;
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break;
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case 8:
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break;
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default:
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return (EINVAL);
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}
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error = vm_set_register(vm, vcpuid, reg, val);
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return (error);
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}
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/*
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* The following simplifying assumptions are made during emulation:
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*
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* - guest is in 64-bit mode
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* - default address size is 64-bits
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* - default operand size is 32-bits
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*
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* - operand size override is not supported
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*
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* - address size override is not supported
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*/
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static int
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emulate_mov(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
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mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
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{
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int error, size;
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enum vm_reg_name reg;
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uint8_t byte;
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uint64_t val;
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size = 4;
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error = EINVAL;
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switch (vie->op.op_byte) {
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case 0x88:
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/*
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* MOV byte from reg (ModRM:reg) to mem (ModRM:r/m)
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* 88/r: mov r/m8, r8
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* REX + 88/r: mov r/m8, r8 (%ah, %ch, %dh, %bh not available)
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*/
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size = 1;
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error = vie_read_bytereg(vm, vcpuid, vie, &byte);
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if (error == 0)
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error = memwrite(vm, vcpuid, gpa, byte, size, arg);
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break;
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case 0x89:
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/*
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* MOV from reg (ModRM:reg) to mem (ModRM:r/m)
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* 89/r: mov r/m32, r32
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* REX.W + 89/r mov r/m64, r64
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*/
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if (vie->rex_w)
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size = 8;
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reg = gpr_map[vie->reg];
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error = vie_read_register(vm, vcpuid, reg, &val);
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if (error == 0) {
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val &= size2mask[size];
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error = memwrite(vm, vcpuid, gpa, val, size, arg);
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}
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break;
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case 0x8B:
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/*
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* MOV from mem (ModRM:r/m) to reg (ModRM:reg)
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* 8B/r: mov r32, r/m32
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* REX.W 8B/r: mov r64, r/m64
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*/
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if (vie->rex_w)
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size = 8;
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error = memread(vm, vcpuid, gpa, &val, size, arg);
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if (error == 0) {
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reg = gpr_map[vie->reg];
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error = vie_update_register(vm, vcpuid, reg, val, size);
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}
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break;
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case 0xC7:
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/*
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* MOV from imm32 to mem (ModRM:r/m)
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* C7/0 mov r/m32, imm32
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* REX.W + C7/0 mov r/m64, imm32 (sign-extended to 64-bits)
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*/
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val = vie->immediate; /* already sign-extended */
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if (vie->rex_w)
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size = 8;
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if (size != 8)
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val &= size2mask[size];
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error = memwrite(vm, vcpuid, gpa, val, size, arg);
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break;
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default:
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break;
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}
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return (error);
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}
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static int
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emulate_and(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
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mem_region_read_t memread, mem_region_write_t memwrite, void *arg)
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{
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int error, size;
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enum vm_reg_name reg;
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uint64_t val1, val2;
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size = 4;
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error = EINVAL;
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switch (vie->op.op_byte) {
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case 0x23:
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/*
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* AND reg (ModRM:reg) and mem (ModRM:r/m) and store the
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* result in reg.
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*
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* 23/r and r32, r/m32
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* REX.W + 23/r and r64, r/m64
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*/
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if (vie->rex_w)
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size = 8;
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/* get the first operand */
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reg = gpr_map[vie->reg];
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error = vie_read_register(vm, vcpuid, reg, &val1);
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if (error)
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break;
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/* get the second operand */
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error = memread(vm, vcpuid, gpa, &val2, size, arg);
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if (error)
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break;
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/* perform the operation and write the result */
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val1 &= val2;
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error = vie_update_register(vm, vcpuid, reg, val1, size);
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break;
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case 0x81:
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/*
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* AND reg (ModRM:reg) with immediate and store the
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* result in reg
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*
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* 81/ and r/m32, imm32
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* REX.W + 81/ and r/m64, imm32 sign-extended to 64
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*
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* Currently, only the AND operation of the 0x81 opcode
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* is implemented (ModRM:reg = b100).
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*/
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if ((vie->reg & 7) != 4)
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break;
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if (vie->rex_w)
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size = 8;
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/* get the first operand */
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error = memread(vm, vcpuid, gpa, &val1, size, arg);
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if (error)
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break;
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/*
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* perform the operation with the pre-fetched immediate
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* operand and write the result
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*/
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val1 &= vie->immediate;
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error = memwrite(vm, vcpuid, gpa, val1, size, arg);
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break;
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default:
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break;
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}
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return (error);
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}
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int
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vmm_emulate_instruction(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
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mem_region_read_t memread, mem_region_write_t memwrite,
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void *memarg)
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{
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int error;
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if (!vie->decoded)
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return (EINVAL);
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switch (vie->op.op_type) {
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case VIE_OP_TYPE_MOV:
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error = emulate_mov(vm, vcpuid, gpa, vie,
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memread, memwrite, memarg);
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break;
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case VIE_OP_TYPE_AND:
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error = emulate_and(vm, vcpuid, gpa, vie,
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memread, memwrite, memarg);
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break;
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default:
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error = EINVAL;
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break;
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}
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return (error);
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}
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#ifdef _KERNEL
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static void
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vie_init(struct vie *vie)
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{
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bzero(vie, sizeof(struct vie));
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vie->base_register = VM_REG_LAST;
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vie->index_register = VM_REG_LAST;
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}
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static int
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gla2gpa(struct vm *vm, uint64_t gla, uint64_t ptpphys,
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uint64_t *gpa, uint64_t *gpaend)
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{
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vm_paddr_t hpa;
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int nlevels, ptpshift, ptpindex;
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uint64_t *ptpbase, pte, pgsize;
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/*
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* XXX assumes 64-bit guest with 4 page walk levels
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*/
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nlevels = 4;
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while (--nlevels >= 0) {
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/* Zero out the lower 12 bits and the upper 12 bits */
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ptpphys >>= 12; ptpphys <<= 24; ptpphys >>= 12;
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hpa = vm_gpa2hpa(vm, ptpphys, PAGE_SIZE);
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if (hpa == -1)
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goto error;
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ptpbase = (uint64_t *)PHYS_TO_DMAP(hpa);
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ptpshift = PAGE_SHIFT + nlevels * 9;
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ptpindex = (gla >> ptpshift) & 0x1FF;
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pgsize = 1UL << ptpshift;
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|
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pte = ptpbase[ptpindex];
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|
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if ((pte & PG_V) == 0)
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goto error;
|
|
|
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if (pte & PG_PS) {
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if (pgsize > 1 * GB)
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goto error;
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else
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break;
|
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}
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|
|
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ptpphys = pte;
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}
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|
|
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/* Zero out the lower 'ptpshift' bits and the upper 12 bits */
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pte >>= ptpshift; pte <<= (ptpshift + 12); pte >>= 12;
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*gpa = pte | (gla & (pgsize - 1));
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*gpaend = pte + pgsize;
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return (0);
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|
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error:
|
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return (-1);
|
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}
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|
|
|
int
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vmm_fetch_instruction(struct vm *vm, int cpuid, uint64_t rip, int inst_length,
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uint64_t cr3, struct vie *vie)
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|
{
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int n, err;
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uint64_t hpa, gpa, gpaend, off;
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|
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/*
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|
* XXX cache previously fetched instructions using 'rip' as the tag
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|
*/
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|
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if (inst_length > VIE_INST_SIZE)
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panic("vmm_fetch_instruction: invalid length %d", inst_length);
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|
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vie_init(vie);
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|
|
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/* Copy the instruction into 'vie' */
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while (vie->num_valid < inst_length) {
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err = gla2gpa(vm, rip, cr3, &gpa, &gpaend);
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if (err)
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break;
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|
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off = gpa & PAGE_MASK;
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n = min(inst_length - vie->num_valid, PAGE_SIZE - off);
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|
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hpa = vm_gpa2hpa(vm, gpa, n);
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if (hpa == -1)
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break;
|
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|
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bcopy((void *)PHYS_TO_DMAP(hpa), &vie->inst[vie->num_valid], n);
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|
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rip += n;
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vie->num_valid += n;
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}
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|
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if (vie->num_valid == inst_length)
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return (0);
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else
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return (-1);
|
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}
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|
|
|
static int
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vie_peek(struct vie *vie, uint8_t *x)
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|
{
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|
|
|
if (vie->num_processed < vie->num_valid) {
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*x = vie->inst[vie->num_processed];
|
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return (0);
|
|
} else
|
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return (-1);
|
|
}
|
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|
|
static void
|
|
vie_advance(struct vie *vie)
|
|
{
|
|
|
|
vie->num_processed++;
|
|
}
|
|
|
|
static int
|
|
decode_rex(struct vie *vie)
|
|
{
|
|
uint8_t x;
|
|
|
|
if (vie_peek(vie, &x))
|
|
return (-1);
|
|
|
|
if (x >= 0x40 && x <= 0x4F) {
|
|
vie->rex_present = 1;
|
|
|
|
vie->rex_w = x & 0x8 ? 1 : 0;
|
|
vie->rex_r = x & 0x4 ? 1 : 0;
|
|
vie->rex_x = x & 0x2 ? 1 : 0;
|
|
vie->rex_b = x & 0x1 ? 1 : 0;
|
|
|
|
vie_advance(vie);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
decode_opcode(struct vie *vie)
|
|
{
|
|
uint8_t x;
|
|
|
|
if (vie_peek(vie, &x))
|
|
return (-1);
|
|
|
|
vie->op = one_byte_opcodes[x];
|
|
|
|
if (vie->op.op_type == VIE_OP_TYPE_NONE)
|
|
return (-1);
|
|
|
|
vie_advance(vie);
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* XXX assuming 32-bit or 64-bit guest
|
|
*/
|
|
static int
|
|
decode_modrm(struct vie *vie)
|
|
{
|
|
uint8_t x;
|
|
|
|
if (vie_peek(vie, &x))
|
|
return (-1);
|
|
|
|
vie->mod = (x >> 6) & 0x3;
|
|
vie->rm = (x >> 0) & 0x7;
|
|
vie->reg = (x >> 3) & 0x7;
|
|
|
|
/*
|
|
* A direct addressing mode makes no sense in the context of an EPT
|
|
* fault. There has to be a memory access involved to cause the
|
|
* EPT fault.
|
|
*/
|
|
if (vie->mod == VIE_MOD_DIRECT)
|
|
return (-1);
|
|
|
|
if ((vie->mod == VIE_MOD_INDIRECT && vie->rm == VIE_RM_DISP32) ||
|
|
(vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)) {
|
|
/*
|
|
* Table 2-5: Special Cases of REX Encodings
|
|
*
|
|
* mod=0, r/m=5 is used in the compatibility mode to
|
|
* indicate a disp32 without a base register.
|
|
*
|
|
* mod!=3, r/m=4 is used in the compatibility mode to
|
|
* indicate that the SIB byte is present.
|
|
*
|
|
* The 'b' bit in the REX prefix is don't care in
|
|
* this case.
|
|
*/
|
|
} else {
|
|
vie->rm |= (vie->rex_b << 3);
|
|
}
|
|
|
|
vie->reg |= (vie->rex_r << 3);
|
|
|
|
/* SIB */
|
|
if (vie->mod != VIE_MOD_DIRECT && vie->rm == VIE_RM_SIB)
|
|
goto done;
|
|
|
|
vie->base_register = gpr_map[vie->rm];
|
|
|
|
switch (vie->mod) {
|
|
case VIE_MOD_INDIRECT_DISP8:
|
|
vie->disp_bytes = 1;
|
|
break;
|
|
case VIE_MOD_INDIRECT_DISP32:
|
|
vie->disp_bytes = 4;
|
|
break;
|
|
case VIE_MOD_INDIRECT:
|
|
if (vie->rm == VIE_RM_DISP32) {
|
|
vie->disp_bytes = 4;
|
|
vie->base_register = VM_REG_LAST; /* no base */
|
|
}
|
|
break;
|
|
}
|
|
|
|
/* Figure out immediate operand size (if any) */
|
|
if (vie->op.op_flags & VIE_OP_F_IMM)
|
|
vie->imm_bytes = 4;
|
|
else if (vie->op.op_flags & VIE_OP_F_IMM8)
|
|
vie->imm_bytes = 1;
|
|
|
|
done:
|
|
vie_advance(vie);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
decode_sib(struct vie *vie)
|
|
{
|
|
uint8_t x;
|
|
|
|
/* Proceed only if SIB byte is present */
|
|
if (vie->mod == VIE_MOD_DIRECT || vie->rm != VIE_RM_SIB)
|
|
return (0);
|
|
|
|
if (vie_peek(vie, &x))
|
|
return (-1);
|
|
|
|
/* De-construct the SIB byte */
|
|
vie->ss = (x >> 6) & 0x3;
|
|
vie->index = (x >> 3) & 0x7;
|
|
vie->base = (x >> 0) & 0x7;
|
|
|
|
/* Apply the REX prefix modifiers */
|
|
vie->index |= vie->rex_x << 3;
|
|
vie->base |= vie->rex_b << 3;
|
|
|
|
switch (vie->mod) {
|
|
case VIE_MOD_INDIRECT_DISP8:
|
|
vie->disp_bytes = 1;
|
|
break;
|
|
case VIE_MOD_INDIRECT_DISP32:
|
|
vie->disp_bytes = 4;
|
|
break;
|
|
}
|
|
|
|
if (vie->mod == VIE_MOD_INDIRECT &&
|
|
(vie->base == 5 || vie->base == 13)) {
|
|
/*
|
|
* Special case when base register is unused if mod = 0
|
|
* and base = %rbp or %r13.
|
|
*
|
|
* Documented in:
|
|
* Table 2-3: 32-bit Addressing Forms with the SIB Byte
|
|
* Table 2-5: Special Cases of REX Encodings
|
|
*/
|
|
vie->disp_bytes = 4;
|
|
} else {
|
|
vie->base_register = gpr_map[vie->base];
|
|
}
|
|
|
|
/*
|
|
* All encodings of 'index' are valid except for %rsp (4).
|
|
*
|
|
* Documented in:
|
|
* Table 2-3: 32-bit Addressing Forms with the SIB Byte
|
|
* Table 2-5: Special Cases of REX Encodings
|
|
*/
|
|
if (vie->index != 4)
|
|
vie->index_register = gpr_map[vie->index];
|
|
|
|
/* 'scale' makes sense only in the context of an index register */
|
|
if (vie->index_register < VM_REG_LAST)
|
|
vie->scale = 1 << vie->ss;
|
|
|
|
vie_advance(vie);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
decode_displacement(struct vie *vie)
|
|
{
|
|
int n, i;
|
|
uint8_t x;
|
|
|
|
union {
|
|
char buf[4];
|
|
int8_t signed8;
|
|
int32_t signed32;
|
|
} u;
|
|
|
|
if ((n = vie->disp_bytes) == 0)
|
|
return (0);
|
|
|
|
if (n != 1 && n != 4)
|
|
panic("decode_displacement: invalid disp_bytes %d", n);
|
|
|
|
for (i = 0; i < n; i++) {
|
|
if (vie_peek(vie, &x))
|
|
return (-1);
|
|
|
|
u.buf[i] = x;
|
|
vie_advance(vie);
|
|
}
|
|
|
|
if (n == 1)
|
|
vie->displacement = u.signed8; /* sign-extended */
|
|
else
|
|
vie->displacement = u.signed32; /* sign-extended */
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
decode_immediate(struct vie *vie)
|
|
{
|
|
int i, n;
|
|
uint8_t x;
|
|
union {
|
|
char buf[4];
|
|
int8_t signed8;
|
|
int32_t signed32;
|
|
} u;
|
|
|
|
if ((n = vie->imm_bytes) == 0)
|
|
return (0);
|
|
|
|
if (n != 1 && n != 4)
|
|
panic("decode_immediate: invalid imm_bytes %d", n);
|
|
|
|
for (i = 0; i < n; i++) {
|
|
if (vie_peek(vie, &x))
|
|
return (-1);
|
|
|
|
u.buf[i] = x;
|
|
vie_advance(vie);
|
|
}
|
|
|
|
if (n == 1)
|
|
vie->immediate = u.signed8; /* sign-extended */
|
|
else
|
|
vie->immediate = u.signed32; /* sign-extended */
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Verify that the 'guest linear address' provided as collateral of the nested
|
|
* page table fault matches with our instruction decoding.
|
|
*/
|
|
static int
|
|
verify_gla(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie)
|
|
{
|
|
int error;
|
|
uint64_t base, idx;
|
|
|
|
/* Skip 'gla' verification */
|
|
if (gla == VIE_INVALID_GLA)
|
|
return (0);
|
|
|
|
base = 0;
|
|
if (vie->base_register != VM_REG_LAST) {
|
|
error = vm_get_register(vm, cpuid, vie->base_register, &base);
|
|
if (error) {
|
|
printf("verify_gla: error %d getting base reg %d\n",
|
|
error, vie->base_register);
|
|
return (-1);
|
|
}
|
|
}
|
|
|
|
idx = 0;
|
|
if (vie->index_register != VM_REG_LAST) {
|
|
error = vm_get_register(vm, cpuid, vie->index_register, &idx);
|
|
if (error) {
|
|
printf("verify_gla: error %d getting index reg %d\n",
|
|
error, vie->index_register);
|
|
return (-1);
|
|
}
|
|
}
|
|
|
|
if (base + vie->scale * idx + vie->displacement != gla) {
|
|
printf("verify_gla mismatch: "
|
|
"base(0x%0lx), scale(%d), index(0x%0lx), "
|
|
"disp(0x%0lx), gla(0x%0lx)\n",
|
|
base, vie->scale, idx, vie->displacement, gla);
|
|
return (-1);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
vmm_decode_instruction(struct vm *vm, int cpuid, uint64_t gla, struct vie *vie)
|
|
{
|
|
|
|
if (decode_rex(vie))
|
|
return (-1);
|
|
|
|
if (decode_opcode(vie))
|
|
return (-1);
|
|
|
|
if (decode_modrm(vie))
|
|
return (-1);
|
|
|
|
if (decode_sib(vie))
|
|
return (-1);
|
|
|
|
if (decode_displacement(vie))
|
|
return (-1);
|
|
|
|
if (decode_immediate(vie))
|
|
return (-1);
|
|
|
|
if (verify_gla(vm, cpuid, gla, vie))
|
|
return (-1);
|
|
|
|
vie->decoded = 1; /* success */
|
|
|
|
return (0);
|
|
}
|
|
#endif /* _KERNEL */
|