bbe78c2d72
suggested in the SDM. Since some OSes have implemented otherwise don't be too rigorous in enforcing it. Approved by: grehan (co-mentor)
245 lines
5.6 KiB
C
245 lines
5.6 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/smp.h>
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#include <x86/specialreg.h>
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#include <x86/apicreg.h>
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#include <machine/vmm.h>
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#include "vmm_ipi.h"
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#include "vmm_ktr.h"
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#include "vmm_lapic.h"
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#include "vlapic.h"
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/*
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* Some MSI message definitions
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*/
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#define MSI_X86_ADDR_MASK 0xfff00000
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#define MSI_X86_ADDR_BASE 0xfee00000
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#define MSI_X86_ADDR_RH 0x00000008 /* Redirection Hint */
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#define MSI_X86_ADDR_LOG 0x00000004 /* Destination Mode */
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int
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lapic_set_intr(struct vm *vm, int cpu, int vector, bool level)
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{
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struct vlapic *vlapic;
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if (cpu < 0 || cpu >= VM_MAXCPU)
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return (EINVAL);
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if (vector < 32 || vector > 255)
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return (EINVAL);
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vlapic = vm_lapic(vm, cpu);
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if (vlapic_set_intr_ready(vlapic, vector, level))
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vcpu_notify_event(vm, cpu, true);
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return (0);
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}
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int
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lapic_set_local_intr(struct vm *vm, int cpu, int vector)
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{
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struct vlapic *vlapic;
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cpuset_t dmask;
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int error;
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if (cpu < -1 || cpu >= VM_MAXCPU)
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return (EINVAL);
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if (cpu == -1)
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dmask = vm_active_cpus(vm);
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else
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CPU_SETOF(cpu, &dmask);
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error = 0;
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while ((cpu = CPU_FFS(&dmask)) != 0) {
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cpu--;
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CPU_CLR(cpu, &dmask);
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vlapic = vm_lapic(vm, cpu);
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error = vlapic_trigger_lvt(vlapic, vector);
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if (error)
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break;
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}
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return (error);
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}
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int
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lapic_intr_msi(struct vm *vm, uint64_t addr, uint64_t msg)
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{
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int delmode, vec;
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uint32_t dest;
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bool phys;
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VM_CTR2(vm, "lapic MSI addr: %#lx msg: %#lx", addr, msg);
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if ((addr & MSI_X86_ADDR_MASK) != MSI_X86_ADDR_BASE) {
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VM_CTR1(vm, "lapic MSI invalid addr %#lx", addr);
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return (-1);
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}
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/*
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* Extract the x86-specific fields from the MSI addr/msg
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* params according to the Intel Arch spec, Vol3 Ch 10.
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*
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* The PCI specification does not support level triggered
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* MSI/MSI-X so ignore trigger level in 'msg'.
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*
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* The 'dest' is interpreted as a logical APIC ID if both
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* the Redirection Hint and Destination Mode are '1' and
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* physical otherwise.
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*/
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dest = (addr >> 12) & 0xff;
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phys = ((addr & (MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG)) !=
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(MSI_X86_ADDR_RH | MSI_X86_ADDR_LOG));
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delmode = msg & APIC_DELMODE_MASK;
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vec = msg & 0xff;
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VM_CTR3(vm, "lapic MSI %s dest %#x, vec %d",
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phys ? "physical" : "logical", dest, vec);
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vlapic_deliver_intr(vm, LAPIC_TRIG_EDGE, dest, phys, delmode, vec);
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return (0);
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}
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static boolean_t
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x2apic_msr(u_int msr)
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{
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if (msr >= 0x800 && msr <= 0xBFF)
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return (TRUE);
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else
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return (FALSE);
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}
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static u_int
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x2apic_msr_to_regoff(u_int msr)
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{
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return ((msr - 0x800) << 4);
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}
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boolean_t
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lapic_msr(u_int msr)
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{
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if (x2apic_msr(msr) || (msr == MSR_APICBASE))
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return (TRUE);
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else
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return (FALSE);
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}
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int
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lapic_rdmsr(struct vm *vm, int cpu, u_int msr, uint64_t *rval, bool *retu)
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{
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int error;
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u_int offset;
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struct vlapic *vlapic;
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vlapic = vm_lapic(vm, cpu);
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if (msr == MSR_APICBASE) {
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*rval = vlapic_get_apicbase(vlapic);
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error = 0;
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} else {
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offset = x2apic_msr_to_regoff(msr);
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error = vlapic_read(vlapic, 0, offset, rval, retu);
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}
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return (error);
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}
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int
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lapic_wrmsr(struct vm *vm, int cpu, u_int msr, uint64_t val, bool *retu)
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{
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int error;
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u_int offset;
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struct vlapic *vlapic;
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vlapic = vm_lapic(vm, cpu);
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if (msr == MSR_APICBASE) {
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error = vlapic_set_apicbase(vlapic, val);
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} else {
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offset = x2apic_msr_to_regoff(msr);
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error = vlapic_write(vlapic, 0, offset, val, retu);
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}
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return (error);
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}
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int
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lapic_mmio_write(void *vm, int cpu, uint64_t gpa, uint64_t wval, int size,
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void *arg)
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{
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int error;
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uint64_t off;
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struct vlapic *vlapic;
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off = gpa - DEFAULT_APIC_BASE;
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/*
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* Memory mapped local apic accesses must be 4 bytes wide and
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* aligned on a 16-byte boundary.
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*/
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if (size != 4 || off & 0xf)
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return (EINVAL);
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vlapic = vm_lapic(vm, cpu);
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error = vlapic_write(vlapic, 1, off, wval, arg);
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return (error);
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}
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int
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lapic_mmio_read(void *vm, int cpu, uint64_t gpa, uint64_t *rval, int size,
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void *arg)
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{
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int error;
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uint64_t off;
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struct vlapic *vlapic;
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off = gpa - DEFAULT_APIC_BASE;
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/*
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* Memory mapped local apic accesses should be aligned on a
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* 16-byte boundary. They are also suggested to be 4 bytes
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* wide, alas not all OSes follow suggestions.
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*/
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off &= ~3;
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if (off & 0xf)
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return (EINVAL);
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vlapic = vm_lapic(vm, cpu);
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error = vlapic_read(vlapic, 1, off, rval, arg);
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return (error);
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}
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